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M58CR064C Datasheet(PDF) 18 Page - STMicroelectronics |
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M58CR064C Datasheet(HTML) 18 Page - STMicroelectronics |
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18 / 70 page  M58CR064C, M58CR064D, M58CR064P, M58CR064Q 18/70 COMMAND INTERFACE - FACTORY PROGRAM COMMANDS The Factory Program commands are used to speed up programming. They require VPP to be at VPPH except for the Bank Erase command which also operates at VPP = VDD. Refer to Table 7, Fac- tory Program Commands, in conjunction with the following text descriptions. Bank Erase Command The Bank Erase command can be used to erase a bank. It sets all the bits within the selected bank to ’1’. All previous data in the bank is lost. The Bank Erase command will ignore any protected blocks within the bank. If all blocks in the bank are pro- tected then the Bank Erase operation will abort and the data in the bank will not be changed. The Status Register will not output any error. Bank Erase operations can be performed at both VPP = VPPH and VPP = VDD. Two Bus Write cycles are required to issue the command. s The first bus cycle sets up the Bank Erase command. s The second latches the bank address in the internal state machine and starts the Program/ Erase Controller. If the second bus cycle is not Write Bank Erase Confirm (D0h), Status Register bits SR4 and SR5 are set and the command aborts. Erase aborts if Reset turns to VIL. As data integrity cannot be guaranteed when the Erase operation is aborted, the bank must be erased again. Once the command is issued the device outputs the Status Register data when any address within the bank is read. At the end of the operation the bank will remain in Read Status Register mode un- til a Read Array, Read CFI Query or Read Elec- tronic Signature command is issued. During Bank Erase operations the bank being erased will only accept the Read Status Register command, all other commands will be ignored. A Bank Erase operation cannot be suspended. For optimum performance, Bank Erase com- mands should be limited to a maximum of 100 Pro- gram/Erase cycles per Block. After 100 Program/ Erase cycles the internal algorithm will still operate properly but some degradation in performance may occur. Dual operations are not supported during Bank Erase operations and the command cannot be suspended. Typical Erase times are given in Table 14, Pro- gram, Erase Times and Program/Erase Endur- ance Cycles. Double Word Program Command The Double Word Program command improves the programming throughput by writing a page of two adjacent words in parallel. The two words must differ only for the address A0. Programming should not be attempted when VPP is not at VPPH. The command can be executed if VPP is below VPPH but the result is not guaranteed. Three bus write cycles are necessary to issue the Double Word Program command. s The first bus cycle sets up the Double Word Program Command. s The second bus cycle latches the Address and the Data of the first word to be written. s The third bus cycle latches the Address and the Data of the second word to be written and starts the Program/Erase Controller. Read operations in the bank being programmed output the Status Register content after the pro- gramming has started. During Double Word Program operations the bank being programmed will only accept the Read Sta- tus Register command, all other commands will be ignored. Dual operations are not supported during Double Word Program operations. It is not recom- mended to suspend the Double Word Program command. Typical Program times are given in Ta- ble 14, Program, Erase Times and Program/Erase Endurance Cycles. Programming aborts if Reset goes to VIL. As data integrity cannot be guaranteed when the program operation is aborted, the memory locations must be reprogrammed. See Appendix C, Figure 21, Double Word Pro- gram Flowchart and Pseudo Code, for the flow- chart for using the Double Word Program command. Quadruple Word Program Command The Quadruple Word Program command im- proves the programming throughput by writing a page of four adjacent words in parallel. The four words must differ only for the addresses A0 and A1. Programming should not be attempted when VPP is not at VPPH. The command can be executed if VPP is below VPPH but the result is not guaranteed. Five bus write cycles are necessary to issue the Quadruple Word Program command. s The first bus cycle sets up the Double Word Program Command. s The second bus cycle latches the Address and the Data of the first word to be written. |
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