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M58CR064C Datasheet(PDF) 13 Page - STMicroelectronics |
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M58CR064C Datasheet(HTML) 13 Page - STMicroelectronics |
13 / 70 page ![]() 13/70 M58CR064C, M58CR064D, M58CR064P, M58CR064Q COMMAND INTERFACE - STANDARD COMMANDS The following commands are the basic commands used to read, write to and configure the device. Refer to Table 5, Standard Commands, in con- junction with the following text descriptions. Read Array Command The Read Array command returns the addressed bank to Read Array mode. One Bus Write cycle is required to issue the Read Array command and re- turn the addressed bank to Read Array mode. Subsequent read operations will read the ad- dressed location and output the data. A Read Ar- ray command can be issued in one bank while programming or erasing in the other bank. Howev- er if a Read Array command is issued to a bank currently executing a Program or Erase operation the command will be ignored. Read Status Register Command A Bank’s Status Register indicates when a Pro- gram or Erase operation is complete and the suc- cess or failure of operation itself. Issue a Read Status Register command to read the Status Reg- ister content of the addressed Bank. The Read Status Register command can be issued at any time, even during Program or Erase operations. The following Bus Read operations output the con- tent of the Status Register of the addressed bank. The Status Register is latched on the falling edge of E or G signals, and can be read until E or G re- turns to VIH. Either E or G must be toggled to up- date the latched data. See Table 8 for the description of the Status Register Bits. This mode supports asynchronous or single synchronous reads only. Read Electronic Signature Command The Read Electronic Signature command reads the Manufacturer and Device Codes, the Block Locking Status, the Protection Register, and the Configuration Register. The Read Electronic Signature command consists of one write cycle to an address within the bottom bank. A subsequent read operation in the address of the bottom bank will output the Manufacturer Code, the Device Code, the protection Status of Blocks of the bottom bank, the Die Revision Code, the Protection Register, or the Read Configuration Register (see Table 6). If the first write cycle of Read Electronic Signature command is issued to an address within the top bank, a subsequent read operation in an address of the top bank will output the protection Status of blocks of the top bank. The status of the other bank is not affected by the command (see Table 11). This mode supports asynchronous or single synchronous reads only, it does not support page mode or synchronous burst reads. Read CFI Query Command The Read CFI Query command is used to read data from the Common Flash Interface (CFI) memory area located in the bottom bank. The Read CFI Query Command consists of one Bus Write cycle, to an address within the bottom bank. Once the command is issued subsequent Bus Read operations in the same bank read from the Common Flash Interface. If a Read CFI Query command is issued in a bank that is executing a Program or Erase operation the bank will go into Read Status Register mode, sub- sequent Bus Read cycles will output the Status Register and the Program/Erase controller will continue to Program or Erase in the background. When the Program or Erase operation has fin- ished the device will enter Read CFI Query mode. This mode supports asynchronous or single syn- chronous reads only, it does not support page mode or synchronous burst reads. The status of the other banks is not affected by the command (see Table 11). After issuing a Read CFI Query command, a Read Array command should be issued to the addressed bank to return the bank to read mode. See Appendix B, Common Flash Interface, Tables 30, 31, 32, 33, 34 and 35 for details on the infor- mation contained in the Common Flash Interface memory area. Clear Status Register Command The Clear Status Register command can be used to reset (set to ‘0’) error bits SR1, SR3, SR4 and SR5 in the Status Register of the addressed bank. One bus write cycle is required to issue the Clear Status Register command. After the Clear Status Register command the bank returns to Read Array mode. The error bits in the Status Register do not auto- matically return to ‘0’ when a new command is is- sued. The error bits in the Status Register should be cleared before attempting a new Program or Erase command. Block Erase Command The Block Erase command can be used to erase a block. It sets all the bits within the selected block to ’1’. All previous data in the block is lost. If the block is protected then the Erase operation will abort, the data in the block will not be changed and the Status Register will output the error. The Block Erase command can be issued at any moment, re- gardless of whether the block has been pro- grammed or not. Two Bus Write cycles are required to issue the command. s The first bus cycle sets up the Erase command. |
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