M58CR064C datasheet(10/70 Pages) STMICROELECTRONICS

Part #	M58CR064C

Description	64 Mbit 4Mb x 16, Dual Bank, Burst 1.8V Supply Flash Memory

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Manufacturer	STMICROELECTRONICS [STMicroelectronics]

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M58CR064C, M58CR064D, M58CR064P, M58CR064Q

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SIGNAL DESCRIPTIONS

See Figure 2 Logic Diagram and Table 1,Signal

Names, for a brief overview of the signals connect-

ed to this device.

Address Inputs (A0-A21). The Address Inputs

select the cells in the memory array to access dur-

ing Bus Read operations. During Bus Write opera-

tions they control the commands sent to the

Command Interface of the internal state machine.

Data Input/Output (DQ0-DQ15). The Data I/O

outputs the data stored at the selected address

during a Bus Read operation or inputs a command

or the data to be programmed during a Bus Write

operation.

Chip Enable (E). The Chip Enable input acti-

vates the memory control logic, input buffers, de-

coders and sense amplifiers. When Chip Enable is

at VILand Reset/Power-Down is at VIH the device

is in active mode. When Chip Enable is at VIH the

memory is deselected, the outputs are high imped-

ance and the power consumption is reduced to the

stand-by level.

Output Enable (G). The Output Enable controls

the outputs during the Bus Read operation of the

memory.

Write Enable (W). The Write Enable controls the

Bus Write operation of the memory’s Command

Interface. The data and address inputs are latched

on the rising edge of Chip Enable or Write Enable

whichever occurs first.

Write Protect (WP). Write Protect is an input

that gives an additional hardware protection for

each block. When Write Protect is at VIL, the Lock-

Down is enabled and the protection status of the

Locked-Down blocks cannot be changed. When

Write Protect is at VIH, the Lock-Down is disabled

and the Locked-Down blocks can be locked or un-

locked. (refer to Table 13, Lock Status).

Reset/Power-Down (RP). The

Reset/Power-

Down input provides a hardware reset of the mem-

ory, and/or Power-Down functions, depending on

the Configuration Register status. When Reset/

Power-Down is at VIL, the memory is in reset

mode: the outputs are high impedance and if the

Power-Down function is enabled the current con-

sumption is reduced to the Reset Supply Current

IDD2. Refer to Table 18, DC Characteristics - Cur-

rents for the value of IDD2. After Reset all blocks

are in the Locked state and the Configuration Reg-

ister is reset. When Reset/Power-Down is at VIH,

the device is in normal operation. Exiting reset

mode the device enters asynchronous read mode,

but a negative transition of Chip Enable or Latch

Enable is required to ensure valid data outputs.

The Reset/Power-Down pin can be interfaced with

3V logic without any additional circuitry. It can be

tied to VRPH (refer to Table 19, DC Characteris-

tics).

Latch Enable (L). Latch Enable latches the ad-

dress bits on its rising edge. The address latch is

transparent when Latch Enable is at VIL and it is in-

hibited when Latch Enable is at VIH. Latch Enable

can be kept Low (also at board level) when the

Latch Enable function is not required or supported.

Clock (K). The clock input synchronizes the

memory to the microcontroller during synchronous

read operations; the address is latched on a Clock

edge (rising or falling, according to the configura-

tion settings) when Latch Enable is at VIL. Clock is

don't care during asynchronous read and in write

operations.

Wait (WAIT). Wait is an output signal used during

synchronous read to indicate whether the data on

the output bus are valid. This output is high imped-

ance when Chip Enable or Output Enable are at

VIH or Reset/Power-Down is at VIL. It can be con-

figured to be active during the wait cycle or one

clock cycle in advance.

VDD Supply Voltage. VDD provides the power

supply to the internal core of the memory device.

It is the main power supply for all operations

(Read, Program and Erase).

VDDQ Supply Voltage. VDDQ provides the power

supply to the I/O pins and enables all Outputs to

be powered independently from VDD. VDDQ can be

tied to VDD or can use a separate supply.

VPP Program Supply Voltage. VPP is both a

control

input

and

a

power

supply

pin.

In

M58CR064C/D the two functions are selected by

the voltage range applied to the pin. In the

M58CR064P/Q the control feature is disabled.

In M58CR064C/D if VPP is kept in a low voltage

range (0V to VDDQ) VPP is seen as a control input.

In this case a voltage lower than VPPLK gives an

absolute protection against program or erase,

while VPP > VPP1 enables these functions (see Ta-

bles 18 and 19, DC Characteristics for the relevant

values). VPP is only sampled at the beginning of a

program or erase; a change in its value after the

operation has started does not have any effect and

program or erase operations continue.

If VPP is in the range of VPPH it acts as a power

supply pin. In this condition VPP must be stable un-

til the Program/Erase algorithm is completed.

VSS Ground. VSS ground is the reference for the

core supply. It must be connected to the system

ground.

VSSQ Ground. VSSQ ground is the reference for

the input/output circuitry driven by VDDQ. VSSQ

must be connected to VSS

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