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M58CR032C Datasheet(PDF) 22 Page - STMicroelectronics |
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M58CR032C Datasheet(HTML) 22 Page - STMicroelectronics |
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22 / 63 page  M58CR032C, M58CR032D 22/63 Protection Register Program Command The Protection Register Program command is used to Program the 64 bit user One-Time-Pro- grammable (OTP) segment of the Protection Reg- ister. The segment is programmed 16 bits at a time. When shipped all bits in the segment are set to ‘1’. The user can only program the bits to ‘0’. Two write cycles are required to issue the Protec- tion Register Program command. s The first bus cycle sets up the Protection Register Program command. s The second latches the Address and the Data to be written to the Protection Register and starts the Program/Erase Controller. Read operations output the Status Register con- tent after the programming has started. The segment can be protected by programming bit 1 of the Protection Lock Register. Bit 1 of the Pro- tection Lock Register protects bit 2 of the Protec- tion Lock Register. Programming bit 2 of the Protection Lock Register will result in a permanent protection of the Security Block (see Figure 5, Se- curity Block and Protection Register Memory Map). Attempting to program a previously protect- ed Protection Register will result in a Status Reg- ister error. The protection of the Protection Register and/or the Security Block is not revers- ible. The Protection Register Program cannot be sus- pended. See Appendix B, Figure 25, Protection Register Program Flowchart and Pseudo Code, for a flowchart for using the Protection Register Program command. Block Lock Command The Block Lock command is used to lock a block and prevent Program or Erase operations from changing the data in it. All blocks are locked at power-up or reset. Two Bus Write cycles are required to issue the Block Lock command. s The first bus cycle sets up the Block Lock command. s The second Bus Write cycle latches the block address. The lock status can be monitored for each block using the Read Electronic Signature command. Table. 14 shows the Lock Status after issuing a Block Lock command. The Block Lock bits are volatile, once set they re- main set until a hardware reset or power-down/ power-up. They are cleared by a Blocks Unlock command. Refer to the section, Block Locking, for a detailed explanation. See Appendix B, Figure 24, Locking Operations Flowchart and Pseudo Code, for a flowchart for using the Lock command. Block Unlock Command The Blocks Unlock command is used to unlock a block, allowing the block to be programmed or erased. Two Bus Write cycles are required to is- sue the Blocks Unlock command. s The first bus cycle sets up the Block Unlock command. s The second Bus Write cycle latches the block address. The lock status can be monitored for each block using the Read Electronic Signature command. Table. 13 shows the protection status after issuing a Block Unlock command. Refer to the section, Block Locking, for a detailed explanation and Ap- pendix B, Figure 24, Locking Operations Flow- chart and Pseudo Code, for a flowchart for using the Unlock command. Block Lock-Down Command A locked block cannot be Programmed or Erased, or have its protection status changed when WP is low, VIL. When WP is high, VIH, the Lock-Down function is disabled and the locked blocks can be individually unlocked by the Block Unlock com- mand. Two Bus Write cycles are required to issue the Block Lock-Down command. s The first bus cycle sets up the Block Lock command. s The second Bus Write cycle latches the block address. The lock status can be monitored for each block using the Read Electronic Signature command. Locked-Down blocks revert to the locked (and not locked-down) state when the device is reset on power-down. Table. 14 shows the Lock Status af- ter issuing a Block Lock-Down command. Refer to the section, Block Locking, for a detailed explana- tion and Appendix B, Figure 24, Locking Opera- tions Flowchart and Pseudo Code, for a flowchart for using the Lock-Down command. Set Burst Configuration Register Command. The Set Burst Configuration Register command is used to write a new value to the Burst Configura- tion Control Register which defines the burst length, type, X latency, Synchronous/Asynchro- nous Read mode and the valid Clock edge config- uration. Two Bus Write cycles are required to issue the Set Burst Configuration Register command. The first cycle writes the setup command and the address corresponding to the Set Burst Configuration Reg- ister content. The second cycle writes the Burst Configuration Register data and the confirm com- mand. Once the command is issued the memory returns to Read mode as if a Read Memory Array command had been issued. |
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