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M58CR032C Datasheet(PDF) 19 Page - STMicroelectronics |
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M58CR032C Datasheet(HTML) 19 Page - STMicroelectronics |
19 / 63 page ![]() 19/63 M58CR032C, M58CR032D COMMAND INTERFACE All Bus Write operations to the memory are inter- preted by the Command Interface. Commands consist of one or more sequential Bus Write oper- ations. An internal Program/Erase Controller han- dles all timings and verifies the correct execution of the Program and Erase commands. The Pro- gram/Erase Controller provides a Status Register whose output may be read at any time during, to monitor the progress of the operation, or the Pro- gram/Erase states. See Appendix C, Tables 36 and 37, Command Interface States - Lock and Modify Tables, for a summary of the Command In- terface. The Command Interface is reset to Read mode when power is first applied, when exiting from Re- set or whenever VDD is lower than VLKO. Com- mand sequences must be followed exactly. Any invalid combination of commands will reset the de- vice to Read mode. Refer to Table 6, Commands, in conjunction with the text descriptions below. Read Command. The Read command returns the addressed bank to Read mode. One Bus Write cycle is required to issue the Read command and return the ad- dressed Bank to Read mode. Subsequent read operations will read the addressed location and output the data. A Read command can be issued in one bank while programming or erasing in the other bank. However if a Read command is issued to a bank currently executing a program or erase operation the command will be ignored. When a device Reset occurs, the memory defaults to Read mode. Read Status Register Command A bank’s Status Register indicates when a pro- gram or erase operation is complete and the suc- cess or failure of operation itself. Issue a Read Status Register command to read the Status Reg- ister content of the addressed bank. The status of the other bank is not affected by the command. The Read Status Register command can be is- sued at any time, even during program or erase operations. The following Read operations output the content of the Status Register of the addressed bank. The Status Register is latched on the falling edge of E or G signals, and can be read until E or G returns to VIH. Either E or G must be toggled to update the latched data. See Table 15 for the description of the Status Register Bits. This mode supports asynchronous or single synchronous reads only. Read Electronic Signature Command The Read Electronic Signature command reads the Manufacturer and Device Codes and the Block Locking Status, or the Protection Register. The Read Electronic Signature command consists of one write cycle to an address within the bottom bank. A subsequent read operation in the address of the bottom bank will output the Manufacturer Code, the Device Code, the protection Status of Blocks of the bottom bank, the Die Revision Code, the Protection Register, or the Read Configuration Register (see Table 11). If the first write cycle of Read Electronic Signature command is issued to an address within the top bank, a subsequent read operation in an address of the top bank will output the protection Status of blocks of the top bank. The status of the other bank is not affected by the command (see Table 7). This mode supports asynchronous or single synchronous reads only. See Tables 8, 9, 10 and 11 for the valid addresses. Read CFI Query Command The Read CFI Query Command is used to read data from the Common Flash Interface (CFI) Memory Area, located in the bottom bank. One Bus Write cycle, addressed to the bottom bank, is required to issue the Read Query Command. Once the command is issued subsequent Bus Read operations in the bottom bank read from the Common Flash Interface Memory Area. The sta- tus of the top bank is not affected by the command (see Table 7). After issuing a Read CFI Query command, a Read command should be issued to return the bank to read mode. See Appendix B, Common Flash Interface, Tables 29, 30, 31, 32, 33, 34 and 35 for details on the in- formation contained in the Common Flash Inter- face memory area. Clear Status Register Command The Clear Status Register command can be used to reset (set to ‘0’) bits 1, 3, 4 and 5 in the Status Register of the addressed bank’. One bus write cy- cle is required to issue the Clear Status Register command. After the Clear Status Register com- mand the bank returns to read mode. The bits in the Status Register do not automatical- ly return to ‘0’ when a new Program or Erase com- mand is issued. The error bits in the Status Register should be cleared before attempting a new Program or Erase command. Block Erase Command The Block Erase command can be used to erase a block. It sets all the bits within the selected block to ’1’. All previous data in the block is lost. If the block is protected then the Erase operation will abort, the data in the block will not be changed and the Status Register will output the error. It is not necessary to pre-program the block as the Pro- |
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