M58CR032C datasheet(15/63 Pages) STMICROELECTRONICS

Part #	M58CR032C

Description	32 Mbit 2Mb x 16, Dual Bank, Burst 1.8V Supply Flash Memory

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M58CR032C, M58CR032D

Burst Configuration Register

The Burst Configuration Register is used to config-

ure the type of bus access that the memory will

perform.

The Burst Configuration Register is set through

the Command Interface. After a Reset or Power-

Up the device is configured for asynchronous

page read (M15 = 1) and the power save function

is disabled (M10 = 0). The Burst Configuration

Register bits are described in Table 4. They spec-

ify the selection of the burst length, burst type,

burst X latency and the Read operation. Refer to

Figures 7 and 8 for examples of synchronous burst

configurations.

Read Select Bit (M15). The

Read

Select

bit,

M15, is used to switch between asynchronous and

synchronous Bus Read operations. When the

Read Select bit is set to ’1’, Bus Read operations

are asynchronous; when the Read Select but is

set to ’0’, Bus Read operations are synchronous.

Synchronous Burst Read is supported in both pa-

rameter and main blocks and can be performed

across banks.

On reset or power-up the Read Select bit is set

to’1’ for asynchronous access.

X-Latency Bits (M13-M11). The X-Latency bits

are used during Synchronous Bus Read opera-

tions to set the number of clock cycles between

the address being latched and the first data be-

coming available. For correct operation the X-La-

tency bits can only assume the values in Table 4,

Burst Configuration Register.

The correspondence between X-Latency settings

and the maximum sustainable frequency must be

calculated taking into account some system pa-

rameters.

Two conditions must be satisfied:

–(n + 1) tK ≥ tACC - tAVK_CPU + tQVK_CPU

–tK > tKQV + tQVK_CPU

where "n" is the chosen X-Latency configuration

code, tK is the clock period, tAVK_CPU is Clock to

Address Valid, L Low or E Low, whichever occurs

last, and tQVK_CPU is the data setup time required

by the system CPU.

Power-Down Bit (M10). The Power-Down bit is

used to enable or disable the power-down func-

tion. When the Power-Down bit is set to ‘0’ (de-

fault) the power-down function is disabled. When

the Power-Down bit is set to ‘1’ power-down is en-

abled and the device goes into the power-down

state where the IDD supply current is reduced to a

typical figure of IDD2.

if this function is disabled the Reset/Power-Down,

RP, pin causes only a reset of the device and the

supply current is the standby value. The recovery

time after a Reset/Power-Down, RP, pulse is sig-

nificantly longer when power-down is enabled

(see Table 25).

Wait Bit (M8). In burst mode the Wait bit controls

the timing of the Wait output pin, WAIT. When the

Wait bit is ’0’ the Wait output pin is asserted during

the wait state. When the Wait bit is ’1’ (default) the

Wait output pin is asserted one clock cycle before

the wait state.

WAIT is asserted during a continuous burst and

also during a 4 or 8 burst length if no-wrap config-

uration is selected. WAIT is not asserted during

asynchronous reads, single synchronous reads or

during latency in synchronous reads.

Burst Type Bit (M7). The Burst Type bit is used

to configure the sequence of addresses read as

sequential or interleaved. When the Burst Type bit

is ’0’ the memory outputs from interleaved ad-

dresses; when the Burst Type bit is ’1’ (default) the

memory outputs from sequential addresses. See

Tables 5, Burst Type Definition, for the sequence

of addresses output from a given starting address

in each mode.

Valid Clock Edge Bit (M6). The

Valid

Clock

Edge bit, M6, is used to configure the active edge

of the Clock, K, during Synchronous Burst Read

operations. When the Valid Clock Edge bit is ’0’

the falling edge of the Clock is the active edge;

when the Valid Clock Edge bit is ’1’ the rising edge

of the Clock is active.

Wrap Burst Bit (M3). The burst reads can be

confined inside the 4 or 8 Double-Word boundary

(wrap) or overcome the boundary (no wrap). The

Wrap Burst bit is used to select between wrap and

no wrap. When the Wrap Burst bit is set to ‘0’ the

burst read wraps; when it is set to ‘1’ the burst read

does not wrap.

Burst length Bits (M2-M0). The

Burst

Length

bits set the number of Words to be output during a

Synchronous Burst Read operation; 4 words, 8

words or continuous burst, where all the words are

read sequentially.

In continuous burst mode the burst sequence can

cross bank boundaries.

In continuous burst mode or in 4, 8 words no-wrap,

depending on the starting address, the device ac-

tivates the WAIT output to indicate that a delay is

necessary before the data is output.

If the starting address is aligned to a 4 word

boundary no wait states are needed and the WAIT

output is not activated.

If the starting address is shifted by 1,2 or 3 posi-

tions from the four word boundary, WAIT will be

asserted for 1, 2 or 3 clock cycles when the burst

sequence crosses the first 64 word boundary, to

indicate that the device needs an internal delay to

read the successive words in the array. WAIT will

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