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M58CR032C Datasheet(PDF) 10 Page - STMicroelectronics |
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M58CR032C Datasheet(HTML) 10 Page - STMicroelectronics |
10 / 63 page ![]() M58CR032C, M58CR032D 10/63 SIGNAL DESCRIPTIONS See Figure 2 Logic Diagram, and Table 1, Signal Names, for a brief overview of the signals connect- ed to this device. Address Inputs (A0-A20). The Address Inputs select the cells in the memory array to access dur- ing Bus Read operations. During Bus Write opera- tions they control the commands sent to the Command Interface of the internal state machine. The address inputs for the memory array are latched on the rising edge of Latch Enable L. The address latch is transparent when L is at VIL. In synchronous operations the address is also latched on the first rising/falling edge of K (de- pending on clock configuration) when L is low. During a Write operation the address is latched on the rising edge of L or W, whichever occurs first. Data Inputs/Outputs (DQ0-DQ15). The Data In- puts/Outputs output the data stored at the selected address during a Bus Read operation. During Bus Write operations they represent the commands sent to the Command Interface of the internal state machine. Both input data and commands are latched on the rising edge of Write Enable, W. When Chip En- able, E, and Output Enable, G, are at VIL the data bus outputs data from the Memory Array, the Elec- tronic Signature, Manufacturer or Device codes, the Block Protection Status, the Burst Configura- tion Register, the Protection Register or the Status Register. The data bus is high impedance when the chip is deselected, Output Enable, G, is at VIH, or Reset/Power-Down, RP, is at VIL. Chip Enable (E). The Chip Enable input acti- vates the memory control logic, input buffers, de- coders and sense amplifiers. When Chip Enable, E, is at VIH, the memory is deselected and the power consumption is reduced to the standby lev- el. Chip Enable can also be used to control writing to the Command Interface and to the memory ar- ray, while Write Enable, W, remains at VIL. Output Enable (G). The Output Enable gates the outputs through the data buffers during a read op- eration. When Output Enable, G, is at VIH the out- puts are high impedance. Write Enable (W). The Write Enable controls the Bus Write operation of the memory’s Command Interface. Data are latched on the rising edge of Write Enable. Write Protect (WP). Write Protect is an input that gives an additional hardware protection for each block. When Write Protect is at VIL, the Lock-Down is enabled and the protection status of the block cannot be changed. When Write Protect is at VIH, the Lock-Down is disabled and the block can be locked or unlocked. (refer to Table 10, Read Pro- tection Register). Reset/Power-Down (RP). The Reset/Power- Down input provides hardware reset of the memo- ry, and/or Power-Down functions, depending on the Burst Configuration Register status. A Reset or Power-Down of the memory is achieved by pulling RP to VIL for at least tPLPH. When the reset pulse is given, the memory will recover from Power- Down (when enabled) in a minimum of tPHEL, tPHLL or tPHWL (see Table 25 and Figure 16) after the rising edge of RP. After a Reset or Power-Up the device is configured for asynchronous page read (M15=1) and the power save function is dis- abled (M10=0). All blocks are locked after a Reset or Power-Down. Either Chip Enable or Write En- able must be tied to VIH during Power-Up to allow maximum security and the possibility to write a command on the first rising edge of Write Enable. Latch Enable (L). Latch Enable latches the ad- dress bits A0-A20 on its rising edge. The ad- dress latch is transparent when L is at VIL and it is inhibited when L is at VIH. Clock (K). The clock input synchronizes the memory to the microcontroller during burst mode read operation; the address is latched on a K edge (rising or falling, according to the configuration set- tings) when L is at VIL. K is don't care during asyn- chronous page mode read and in write operations. Wait (WAIT). Wait is an output signal used during burst mode read, indicating whether the data on the output bus are valid or a wait state must be in- serted. This output is high impedance when Chip Enable or Output Enable are at VIH or Reset/Pow- er-Down is at VIL. It can be configured to be active during the wait cycle or one clock cycle in ad- vance. VDD Supply Voltage (1.65V to 2V). VDD pro- vides the power supply to the internal core of the memory device. It is the main power supply for all operations (Read, Program and Erase). It ranges from 1.65V to 2.0V. VDDQ Supply Voltage (1.65V to 3.3V). VDDQ provides the power supply to the I/O pins and en- ables all Outputs to be powered independently from VDD. VDDQ can be tied to VDD or it can use a separate supply. It can be powered either from 1.65V to 2.0V or from 1.65V to 3.3V. VPP Program Supply Voltage (12V). VPP is a power supply pin. The Supply Voltage VDD and the Program Supply Voltage VPP can be applied in any order. The pin can also be used as a control input. The two functions are selected by the voltage range applied to the pin. If VPP is kept in a low volt- age range (0V to 2V) VPP is seen as a control in- put. In this case a voltage lower than VPPLK gives an absolute protection against program or erase, |
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