SI5100 datasheet(10/40 Pages) SILABS

Part #	SI5100

Description	SiPHY??OC-48/STM-16 SONET/SDH TRANSCEIVER

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Manufacturer	SILABS [Silicon Laboratories]

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Si5100

10

Rev. 1.1

Table 5. AC Characteristics (Receiver PLL)1

(VDD =1.8 V ± 5%, TA = –20 to 85 °C)

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Jitter Tolerance

(RXDIN = 100 mVPPD, PRBS31)2

JTOL(PP)

f = 10 – 600 Hz

152

——

UIPP

f=0.6–6kHz

152

——

UIPP

f=6–100 kHz

92

——

UIPP

f = 100 kHz–1 MHz

0.4

—

UIPP

f = 1–20 MHz

0.3

—

UIPP

Acquisition Time

TAQ

——

2

ms

Input Reference Clock Frequency

(REFSEL = 1)

RCFREQ

REFRATE = 1

—

155

169

MHz

REFRATE = 0

—

78

84.4

MHz

Reference Clock Duty Cycle

RCDUTY

40

50

60

%

Reference Clock Frequency

Tolerance

RCTOL

–100

—

100

ppm

Frequency Difference at which

Receive PLL goes out of Lock

(REFCLK compared to the

divided down VCO clock)

LOL

610

732

860

ppm

Frequency Difference at which

Receive PLL goes into Lock

(REFCLK compared to the

divided down VCO clock)

LOCK

—

366

240

ppm

Notes:

1. Bellcore specifications: GR-253-CORE, Issue 3, September 2000.

2. Instrument limited.

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