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SI5100 Datasheet(PDF) 1 Page - Silicon Laboratories |
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SI5100 Datasheet(HTML) 1 Page - Silicon Laboratories |
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1 / 40 page  Rev. 1.1 7/04 Copyright © 2004 by Silicon Laboratories Si5100 Si5100 SiPHY™ OC-48/STM-16 SONET/SDH TRANSCEIVER Features Complete, low-power, high-speed, SONET/SDH transceiver with integrated limiting amp, CDR, CMU, and MUX/DEMUX Applications Description The Si5100 is a complete low-power transceiver for high-speed serial communication systems operating between OC-48 and 2.7 Gbps. The receive path consists of a fully-integrated limiting amplifier, clock and data recovery unit (CDR), and 1:16 deserializer. The transmit path combines a low-jitter clock multiplier unit (CMU) with a 16:1 serializer. The CMU uses Silicon Laboratories’ DSPLL technology to provide superior jitter performance while reducing design complexity by eliminating external loop filter components. To simplify BER optimization in long-haul applications, programmable slicing and sample phase adjustment are supported. The Si5100 operates from a single 1.8 V supply over the industrial temperature range (–20 to 85 °C). Functional Block Diagram Data rates supported: OC-48/STM-16 through 2.7 Gbps FEC Low-power operation 1.2 W (typ) DSPLL™ based clock multiplier unit w/ selectable loop filter bandwidths Integrated limiting amplifier Loss-of-signal (LOS) alarm Diagnostic and line loopbacks SONET-compliant loop timed operation Programmable slicing level and sample phase adjustment LVDS/LVPECL compatible interface Single supply 1.8 V operation 15 x 15 mm BGA package SONET/SDH transmission systems Optical transceiver modules SONET/SDH test equipment TXCLKOUT RXDOUT[15:0] RXCLK TXDOUT RXDIN TXDIN[15:0] SLICELVL PHASEADJ BWSEL[1:0] TXCLK16IN REFCLK Limiting AMP CDR DSPLLTM TX CMU ÷ Line Loopback Diagnostic Loopback Ordering Information: See page 35. Si5100 Bottom View |
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