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MB90330A Datasheet(PDF) 82 Page - Fujitsu Component Limited. |
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MB90330A Datasheet(HTML) 82 Page - Fujitsu Component Limited. |
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82 / 120 page  MB90330A Series 82 20. Low power consumption (standby) mode The F2MC-16LX can be set to save power consumption by selecting and setting the low power consumption mode. • CPU operation mode and functional description • Register list CPU operating clock Operation mode Description PLL clock Normal run The CPU and peripheral resources operate at the clock frequency obtained by PLL multiplication of oscillator clock (HCLK) frequency. Sleep Only peripheral resources operate at the clock frequency obtained by PLL multiplica- tion of the oscillator clock (HCLK) . Time-base timer Only the time-base timer operates at the clock frequency obtained by PLL multiplica- tion of the oscillator clock (HCLK) frequency. Stop The CPU and peripheral resources are suspended with the oscillator clock stopped. Main clock Normal run The CPU and peripheral resources operate at the clock frequency obtained by divid- ing the oscillator clock (HCLK) frequency by two. Sleep Only peripheral resources operate at the clock frequency obtained by dividing the oscillator clock (HCLK) frequency by two. Time-base timer Only the time-base timer operates at the clock frequency obtained by dividing the oscillator clock (HCLK) frequency by two. Stop The CPU and peripheral resources are suspended with the oscillator clock stopped. Sub clock Normal run The CPU and peripheral resources operate at the clock frequency obtained by dividing the sub clock (SCLK) frequency by four. Sleep Only peripheral resources operate at the clock frequency obtained by dividing the sub clock (SCLK) frequency by four. Watch mode Only the watch timer operates at the clock frequency obtained by dividing the sub clock (SCLK) frequency by four. Stop The CPU and peripheral resources are suspended with the sub clock stopped. CPU intermittent operation mode Normal run The halved or PLL-multiplied oscillator clock (HCLK) frequency or the sub clock (SCLK) frequency is used for operation while being decimated in a certain period. Low power consumption mode control register (LPMCR) bit Initial Value Address : 0000A0H 00011000B ( W ) ( R/W ) ( W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) 76 5 4 3 2 1 0 SLP ( W ) STP SPL RST TMD CG1 CG0 Reserved |
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