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MB90330A Datasheet(PDF) 79 Page - Fujitsu Component Limited. |
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MB90330A Datasheet(HTML) 79 Page - Fujitsu Component Limited. |
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79 / 120 page  MB90330A Series 79 17. Address matching detection function When the address is equal to the value set in the address detection register, the instruction code to be read into the CPU is forcibly replaced with the INT9 instruction code (01H). As a result, the CPU executes the INT9 instruction when executing the set instruction. By performing processing by the INT#9 interrupt routine, the program patch function is enabled. 2 address detection registers are provided, for each of which there is an interrupt enable bit. When the address matches the value set in the address detection register with the interrupt enable bit set to 1, the instruction code to be read into the CPU is forcibly replaced with the INT9 instruction code. • Register list • Program address detect register 0 to 2 (PADR0) • Program address detect register 3 to 5 (PADR1) • Program address detection control status register (PACSR) PADR0 (lower) bit Initial Value XXXXXXXXB Address : 001FF0H PADR0 (middle) bit Initial Value XXXXXXXXB Address : 001FF1H PADR0 (upper) bit Initial Value XXXXXXXXB Address : 001FF2H PADR1 (lower) bit Initial Value XXXXXXXXB Address : 001FF3H PADR1 (middle) bit Initial Value XXXXXXXXB Address : 001FF4H PADR1 (upper) bit Initial Value XXXXXXXXB Address : 001FF5H PACSR bit Initial Value 00000000B Address : 00009EH (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) 76 5 4 32 1 0 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) 15 14 13 12 11 10 9 8 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) 76 5 4 32 1 0 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) 15 14 13 12 11 10 9 8 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) 76 5 4 32 1 0 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) 15 14 13 12 11 10 9 8 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) 76 5 4 3 2 1 0 (R/W) ADIE ADDE Reserved Reserved Reserved Reserved Reserved Reserved R/W : Readable and Writable X : Undefined |
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