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MB90330A Datasheet(PDF) 76 Page - Fujitsu Component Limited. |
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MB90330A Datasheet(HTML) 76 Page - Fujitsu Component Limited. |
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76 / 120 page  MB90330A Series 76 15. µDMAC µDMAC is simple DMA with the function equal with EI2OS. It has 16 channels DMA transfer channels with the following features. • Performs automatic data transfer between the peripheral resource (I/O) and memory • The program execution of CPU stops in the DMA start-up • Capable of selecting whether to increment the transfer source and destination addresses • DMA transfer is controlled by the DMA enable register, DMA stop status register, DMA status register, and descriptor. • A STOP request is available for stopping DMA transfer from the resource. Upon completion of DMA transfer, the flag bit corresponding to the transfer completed channel in the DMA status register is set and a termination interrupt is output to the transfer controller. • Register list (Continued) DMA enable register upper (DERH) DMA enable register lower (DERL) DMA stop status register (DSSR) DMA status register upper (DSRH) DMA status register lower (DSRL) DMA descriptor channel specification register (DCSR) * : The DSSR is lower when the STP bit of DCSR in the DSSR is “0”. The DSSR is upper when the STP bit of DCSR in the DSSR is “1”. bit Initial Value Address : 0000ADH 00000000B bit Initial Value Address : 0000ACH 00000000B bit Initial Value Address : 0000A4H 00000000B * bit Initial Value Address : 00009DH 00000000B bit Initial Value Address : 00009CH 00000000B bit Initial Value Address : 00009BH 00000000B ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) 15 14 13 12 11 10 9 8 EN14 ( R/W ) EN15 EN13 EN12 EN11 EN10 EN9 EN8 ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) 76 5 4 3 2 1 0 EN6 ( R/W ) EN7 EN5 EN4 EN3 EN2 EN1 EN0 76 5 4 3 2 1 0 STP6 STP14 STP7 STP15 STP5 STP13 STP4 STP12 STP3 STP11 STP2 STP10 STP1 STP9 STP0 STP8 ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) 15 14 13 12 11 10 9 8 DTE14 DTE15 DTE13 DTE12 DTE11 DTE10 DTE9 DTE8 ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) 76 5 4 3 2 1 0 DTE6 ( R/W ) DTE7 DTE5 DTE4 DTE3 DTE2 DTE1 DTE0 ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) 15 14 13 12 11 10 9 8 ( R/W ) STP DCSR3 DCSR2 DCSR1 DCSR0 Reserved Reserved Reserved |
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