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MB90330A Datasheet(PDF) 44 Page - Fujitsu Component Limited. |
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MB90330A Datasheet(HTML) 44 Page - Fujitsu Component Limited. |
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44 / 120 page  MB90330A Series 44 5. 16-bit reload timer The 16-bit reload timer has the internal clock mode to decrement in synchronization with 3 different internal clocks and the event count mode to decrement upon detection of an arbitrary edge of the pulse input to the external pin. Either can be selected. This timer defines when the count value changes from 0000H to FFFFH as an underflow. The timer therefore causes an underflow when the count reaches [reload register setting + 1]. Either mode can be selected for the count operation from the reload mode which repeats the count by reloading the count setting value at the underflow occurrence or the one-shot mode which stops the count at the underflow occurrence. The interrupt can be generated at the counter underflow occurrence so as to correspond to the DTC. • Register list • TMCSR (Timer control status register 0 to 2) Timer control status register (upper) (TMCSR0 to TMCSR2) Timer control status register (lower) (TMCSR0 to TMCSR2) • 16-bit timer register/16-bit reload register TMR0 to TMR2/TMRLR0 to TMRLR2 (upper) TMR0 to TMR2/TMRLR0 to TMRLR2 (lower) Address : bit 000063H 000067H 00006BH Initial Value XXXX0000B Address : bit 000062H 000066H 00006AH Initial Value 00000000B Address : bit 000065H 000069H 00006DH Initial Value XXXXXXXXB Address : bit 000064H 000068H 00006CH Initial Value XXXXXXXXB ( ⎯ )( ⎯ )( ⎯ ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) 15 14 13 12 11 10 9 8 ⎯ ( ⎯ ) ⎯⎯ ⎯ CSL1 CSL0 MOD2 MOD1 ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) 76 5 4 3 2 1 0 OUTE ( R/W ) MOD0 OUTL RELD INTE UF CNTE TRG ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) 15 14 13 12 11 10 9 8 D14 ( R/W ) D15 D13 D12 D11 D10 D09 D08 ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) 76 5 4 32 1 0 D06 ( R/W ) D07 D05 D04 D03 D02 D01 D00 |
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Similar Description - MB90330A |
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