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MB90330A Datasheet(PDF) 41 Page - Fujitsu Component Limited. |
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MB90330A Datasheet(HTML) 41 Page - Fujitsu Component Limited. |
41 / 120 page ![]() MB90330A Series 41 3. Watchdog timer The watchdog timer is timer counter provided for measure of program runaway. It is a 2-bit counter operating with an output of the timebase timer or watch timer as the count clock and resets the CPU when the counter is not cleared for a preset period of time after start. • Interval time of watchdog timer Notes : • The maximum and minimum time intervals for the watchdog timer depend on the counter clear timing. • The watchdog timer contains a 2-bit counter that counts the carry-up signal from the time-base timer or watch timer. • Interval time of watchdog timer is longer than the set time during the following conditions. - When clearing the timebase timer during operation on oscillation (HCLK) - When clearing the watch timer during operation on sub clock (SCLK) • Events that stop the watchdog timer • Stop due to a power-on reset • Watchdog reset • Clear factor of watchdog timer • External reset input by RST pin • Writing “0” to the software reset bit • Writing “0” to the watchdog timer control bit (second and subsequent times) • Transition to sleep mode (clearing the watchdog timer to suspend counting) • Transition to time-base timer mode (clearing the watchdog timer to suspend counting) • Transition to stop mode (clearing the watchdog timer to suspend counting) HCLK : Oscillation clock(6 MHz) SCLK : Sub clock(8 kHz) Min Max Clock cycle Approx. 2.39 ms Approx. 3.07 ms (214 ± 211) /HCLK Approx. 9.56 ms Approx. 12.29 ms (216 ± 213) /HCLK Approx. 38.23 ms Approx. 49.15 ms (218 ± 215) /HCLK Approx. 305.83 ms Approx. 393.22 ms (221 ± 218) /HCLK Approx. 0.448 s Approx. 0.576 s (212 ± 29) /SCLK Approx. 3.584 s Approx. 4.608 s (215 ± 212) /SCLK Approx. 7.168 s Approx. 9.216 s (216 ± 213) /SCLK Approx. 14.336 s Approx. 18.432 s (217 ± 214) /SCLK |
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