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MB90330A Datasheet(PDF) 35 Page - Fujitsu Component Limited. |
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MB90330A Datasheet(HTML) 35 Page - Fujitsu Component Limited. |
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35 / 120 page  MB90330A Series 35 • Register list (port direction register) • When each pin is serving as a port, the corresponding pin is controlled as follows : 0 : Input mode 1 : Output mode This bit becomes 0 after a reset. Note : If these registers are accessed by a read modify write instruction (such as a bit set instruction) , the bits manipulated by the instruction are set to prescribed values but those other bits in output registers which have been set for input are rewritten to current input values of the pins. When switching a pin from input port to output port, therefore, write a desired value in the PDR first, then set the DDR to switch the pin for output. DDR0 bit Initial Value Access Address : 000010H 00000000B R/W DDR1 bit Address : 000011H 00000000B R/W DDR2 bit Address : 000012H 00000000B R/W DDR3 bit Address : 000013H 00000000B R/W DDR4 bit Address : 000014H 00000000B R/W DDR5 bit Address : 000015H 00000000B R/W DDR6 bit Address : 000016H 00000000B R/W DDR7 bit Address : 000017H 00000000B R/W DDR8 bit Address : 000018H 00000000B R/W DDR9 bit Address : 000019H -0000000B R/W DDRA bit Address : 00001AH 00000000B R/W DDRB bit Address : 00000DH -0000000B R/W 76 5 4 3 2 1 0 D06 D07 D05 D04 D03 D02 D01 D00 15 14 13 12 11 10 9 8 D16 D17 D15 D14 D13 D12 D11 D10 76 5 4 3 2 1 0 D26 D27 D25 D24 D23 D22 D21 D20 15 14 13 12 11 10 9 8 D36 D37 D35 D34 D33 D32 D31 D30 76 5 4 3 2 1 0 D46 D47 D45 D44 D43 D42 D41 D40 15 14 13 12 11 10 9 8 D56 D57 D55 D54 D53 D52 D51 D50 76 5 4 3 2 1 0 D66 D67 D65 D64 D63 D62 D61 D60 15 14 13 12 11 10 9 8 D75 D74 D73 D72 D71 D70 D76 D77 76 5 4 3 2 1 0 D84 D83 D82 D81 D80 D87 D86 D85 15 14 13 12 11 10 9 8 D91 D90 ⎯ D96 D95 D94 D93 D92 76 5 4 3 2 1 0 DA1 DA0 DA7 DA6 DA5 DA4 DA3 DA2 15 14 13 12 11 10 9 8 DB1 DB0 ⎯ DB6 DB5 DB4 DB3 DB2 |
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