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MB90330A Datasheet(PDF) 34 Page - Fujitsu Component Limited. |
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MB90330A Datasheet(HTML) 34 Page - Fujitsu Component Limited. |
34 / 120 page MB90330A Series 34 • Register list (port data register) * : R/W access to I/O ports is a bit different in behavior from R/W access to memory as follows : • Input mode Read : The level at the relevant pin is read. Write : Data is written to the output latch. • Output mode Read : The data register latch value is read. Write : Data is output to the relevant pin. PDR0 bit Initial Value Access Address : 000000H XXXXXXXXB R/W* PDR1 bit Address : 000001H XXXXXXXXB R/W* PDR2 bit Address : 000002H XXXXXXXXB R/W* PDR3 bit Address : 000003H XXXXXXXXB R/W* PDR4 bit Address : 000004H XXXXXXXXB R/W* PDR5 bit Address : 000005H XXXXXXXXB R/W* PDR6 bit Address : 000006H XXXXXXXXB R/W* PDR7 bit Address : 000007H XXXXXXXXB R/W* PDR8 bit Address : 000008H XXXXXXXXB R/W* PDR9 bit Address : 000009H - XXXXXXXB R/W* PDRA bit Address : 00000AH XXXXXXXXB R/W* PDRB bit Address : 00000CH - XXXXXXXB R/W* 76 5 4 3 2 1 0 P06 P07 P05 P04 P03 P02 P01 P00 15 14 13 12 11 10 9 8 P16 P17 P15 P14 P13 P12 P11 P10 76 5 4 3 2 1 0 P26 P27 P25 P24 P23 P22 P21 P20 15 14 13 12 11 10 9 8 P36 P37 P35 P34 P33 P32 P31 P30 76 5 4 3 2 1 0 P46 P47 P45 P44 P43 P42 P41 P40 15 14 13 12 11 10 9 8 P56 P57 P55 P54 P53 P52 P51 P50 76 5 4 3 2 1 0 P66 P65 P64 P63 P62 P61 P60 P67 15 14 13 12 11 10 9 8 P76 P75 P74 P73 P72 P71 P70 P77 76 5 4 3 2 1 0 P84 P83 P82 P81 P80 P87 P86 P85 15 14 13 12 11 10 9 8 P91 P90 ⎯ P96 P95 P94 P93 P92 76 5 4 3 2 1 0 PA1 PA0 PA7 PA6 PA5 PA4 PA3 PA2 76 5 4 3 2 1 0 PB1 PB0 ⎯ PB6 PB5 PB4 PB3 PB2 |
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