TLC0831C, TLC0831I

TLC0832C, TLC0832I

8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL

SLAS107B – JANUARY 1995 – REVISED APRIL 1996

3

POST OFFICE BOX 655303

functional description

The TLC0831 and TLC0832 use a sample-data-comparator structure that converts differential analog inputs

by a successive-approximation routine. The input voltage to be converted is applied to an input terminal and

is compared to ground (single ended), or to an adjacent input (differential). The TLC0832 input terminals can

be assigned a positive (+) or negative (–) polarity. The TLC0831 contains only one differential input channel with

fixed polarity assignment; therefore it does not require addressing. The signal can be applied differentially,

between IN+ and IN–, to the TLC0831 or can be applied to IN+ with IN– grounded as a single ended input. When

the signal input applied to the assigned positive terminal is less than the signal on the negative terminal, the

converter output is all zeros.

Channel selection and input configuration are under software control using a serial-data link from the controlling

processor. A serial-communication format allows more functions to be included in a converter package with no

increase in size. In addition, it eliminates the transmission of low-level analog signals by locating the converter

at the analog sensor and communicating serially with the controlling processor. This process returns noise-free

digital data to the processor.

A conversion is initiated by setting CS low, which enables all logic circuits. CS must be held low for the complete

conversion process. A clock input is then received from the processor. An interval of one clock period is

automatically inserted to allow the selected multiplexed channel to settle. DO comes out of the high-impedance

state and provides a leading low for one clock period of multiplexer settling time. The SAR comparator compares

successive outputs from the resistive ladder with the incoming analog signal. The comparator output indicates

whether the analog input is greater than or less than the resistive-ladder output. As the conversion proceeds,

conversion data is simultaneously output from DO, with the most significant bit (MSB) first. After eight clock

periods, the conversion is complete. When CS goes high, all internal registers are cleared. At this time, the

output circuits go to the high-impedance state. If another conversion is desired, CS must make a high-to-low

transition followed by address information.

A TLC0832 input configuration is assigned during the multiplexer-addressing sequence. The multiplexer

address shifts into the converter through the data input (DI) line. The multiplexer address selects the analog

inputs to be enabled and determines whether the input is single ended or differential. When the input is

differential, the polarity of the channel input is assigned. In addition to selecting the differential mode, the polarity

may also be selected. Either channel of the channel pair may be designated as the negative or positive input.

On each low-to-high transition of the clock input, the data on DI is clocked into the multiplexer-address shift

register. The first logic high on the input is the start bit. A 2-bit assignment word follows the start bit on the

TLC0832. On each successive low-to-high transition of the clock input, the start bit and assignment word are

shifted through the shift register. When the start bit is shifted into the start location of the multiplexer register,

the input channel is selected and conversion starts. The TLC0832 DI terminal to the multiplexer shift register

is disabled for the duration of the conversion.

The TLC0832 outputs the least-significant-bit (LSB) first data after the MSB-first data stream. The DI and DO

terminals can be tied together and controlled by a bidirectional processor I/O bit received on a single wire. This

is possible because DI is only examined during the multiplexer-addressing interval and DO is still in the

high-impedance state.