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S1D13706F00A Datasheet(PDF) 12 Page - Epson Company |
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S1D13706F00A Datasheet(HTML) 12 Page - Epson Company |
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12 / 94 page  6 EPSON S1D13305 Series Technical Manual 5.2.4. Display memory control The S1D13305 series can directly access static RAM and PROM. The designer may use a mixture of these two types of memory to achieve an optimum trade-off be- tween low cost and low power consumption. Pin Name Function 8080 family interface A0 RD WR Function 0 0 1 Status flag read 1 0 1 Display data and cursor address read 0 1 0 Display data and parameter write 1 1 0 Command write 6800 family interface A0 R/W E Function 0 1 1 Status flag read 1 1 1 Display data and cursor address read 0 0 1 Display data and parameter write 1 0 1 Command write When the 8080 family interface is selected, this signal acts as the active-LOW read strobe. The S1D13305 series output buffers are enabled when this signal is active. When the 6800 family interface is selected, this signal acts as the active-HIGH enable clock. Data is read from or written to the S1D13305 series when this clock goes HIGH. When the 8080 family interface is selected, this signal acts as the active-LOW write strobe. The bus data is latched on the rising edge of this signal. When the 6800 family interface is selected, this signal acts as the read/write control signal. Data is read from the S1D13305 series if this signal is HIGH, and written to the S1D13305 series if it is LOW. Chip select. This active-LOW input enables the S1D13305 series. It is usually connected to the output of an address decoder device that maps the S1D13305 series into the memory space of the controlling microprocessor. This active-LOW input performs a hardware reset on the S1D13305 series. It is a Schmitt-trigger input for enhanced noise immunity; however, care should be taken to ensure that it is not triggered if the supply voltage is lowered. WR or R/W CS RES RD or E A0 VA0 to VA15 16-bit display memory address. When accessing character generator RAM or ROM, VA0 to VA3, reflect the lower 4 bits of the S1D13305 series’s row counter. VD0 to VD7 8-bit tristate display memory data bus. These pins are enabled when VR/W is LOW. VCE Active-LOW static memory standby control signal. VCE can be used with CS. VWR Active-LOW display memory write control output. Pin Name Function VRD Active-LOW display memory read control output. PIN DESCRIPTION |
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