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S1D13706F00A Datasheet(PDF) 51 Page - Epson Company |
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S1D13706F00A Datasheet(HTML) 51 Page - Epson Company |
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51 / 94 page  S1D13305 Series EPSON 45 Technical Manual 9.2.3. Display scan timing Figure 32 shows the basic timing of the S1D13305 series. One display memory read cycle takes nine periods of the system clock, φ0 (fOSC ). This cycle repeats (C/R + 1) times per display line. When reading, the display memory pauses at the end of each line for (TC/R - C/R) display memory read cycles, though the LCD drive signals are still generated. TC/R may be set to any value within the constraints imposed by C/R, fOSC , fFR , and the size of the LCD panel, and it may be used to fine tune the frame frequency. The micropro- cessor may also use this pause to access the display memory data. Figure 32. Display memory basic read cycle T0 T1 T2 Display read cycle interval Graphics read interval Character read interval Character generator read interval φ0 VCE VA Figure 33. Relationship between TC/R and C/R Frame period Display period Divider frequency period TC/R C/R O O O • • • • • O R R R R Line 1 2 3 (L/F) LP Note: The divider adjustment interval (R) applies to both the upper and lower screens even if W/S = 1. In this case, LP is active only at the end of the lower screen’s display interval. DISPLAY CONTROL FUNCTIONS |
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