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S1D13706F00A Datasheet(PDF) 18 Page - Epson Company |
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S1D13706F00A Datasheet(HTML) 18 Page - Epson Company |
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18 / 94 page  12 EPSON S1D13305 Series Technical Manual 6.3.3. Display memory read timing EXT Φ0 VCE VA0 to VA15 VR/W VD0 to VD7 tC tW tCE tW tAHC tASC tCYR tRCS tCEA tRCH tCE3 tOH2 tACV Signal Symbol Parameter VDD = 4.5 to 5.5V VDD = 2.7 to 4.5V Unit Condition Min. Max. Min. Max. EXT φ0tC Clock period 100 — 125 — ns tW VCE HIGH-level pulsewidth tC – 50 — tC – 50 — ns VCE tCE VCE LOW-level pulsewidth 2tC – 30 — 2tC – 30 — ns tCYR Read cycle time 3tC —3tC —ns tASC Address setup time to tC – 70 — tC – 100 — ns falling edge of VCE tAHC Address hold time from 2tC – 30 — 2tC – 40 — ns falling edge of VCE tRCS Read cycle setup time to tC – 45 — tC – 60 — ns VRD falling edge of VCE tRCH Read cycle hold time 0.5tC — 0.5tC —ns from rising edge of VCE tACV Address access time — 3tC – 100 — 3tC – 115 ns VD0 to tCEA VCE access time — 2tC – 80 — 2tC – 90 ns VD7 tOH2 Output data hold time 0 — 0 — ns tCE3 VCE to data off time 0 — 0 — ns VA0 to VA15 CL = 100 pF Ta = –20 to 75 °C SPECIFICATIONS |
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