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S1D13706F00A Datasheet(PDF) 15 Page - Epson Company |
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S1D13706F00A Datasheet(HTML) 15 Page - Epson Company |
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15 / 94 page  S1D13305 Series EPSON 9 Technical Manual Notes 1. D0 to D7, A0, CS, RD, WR, VD0 to VD7, VA0 to VA15, VRD, VWR and VCE are TTL-level inputs. 2. SEL1 is CMOS-level inputs. YD, XD0 to XD3, XSCL, LP, WF, YDIS are CMOS-level outputs. 3. RES is a Schmitt-trigger input. The pulsewidth on RES must be at least 200 µs. Note that pulses of more than a few seconds will cause DC voltages to be applied to the LCD panel. 4. fOSC = 10 MHz, no load (no display memory), internal character generator, 256 × 200 pixel display. The operating supply current can be reduced by approximately 1 mA by setting both CLO and the display OFF. 5. VD0 to VD7 and D0 to D7 have internal feedback circuits so that if the inputs become high-impedance, the input state immediately prior to that is held. Because of the feedback circuit, input current flow occurs when the inputs are in an intermediate state. 6. Because the oscillator circuit input bias current is in the order of µA, design the printed circuit board so as to reduce leakage currents. VDD = 2.7 to 4.5 V, VSS = 0 V, Ta = –20 to 75˚C unless otherwise noted Parameter Symbol Condition Rating Unit Min. Typ. Max. Supply voltage VDD 2.7 3.5 4.5 V Register data retention voltage VOH 2.0 — 6.0 V Input leakage current ILI VI = VDD. See note 5. — 0.05 2.0 µA Output leakage current ILO VI = VSS. See note 5. — 0.10 5.0 µA Operating supply current Iopr VDD = 3.5 V. See note 4. — 3.5 — mA See note 4. — — 7.0 Quiescent supply current IQ Sleep mode, — 0.05 20.0 µA VOSC1 = VCS = VRD = VDD Oscillator frequency fOSC Measured at crystal, 1.0 — 8.0 MHz External clock frequency fCL 47.5% duty cycle. 1.0 — 8.0 MHz Oscillator feedback resistance Rf See note 6. 0.7 — 3.0 M Ω TTL HIGH-level input voltage VIHT See note 1. 0.5 VDD —VDD V LOW-level input voltage VILT See note 1. VSS — 0.2 VDD V HIGH-level output voltage VOHT IOH = –3.0 mA. See note 1. 2.4 — — V LOW-level output voltage VOLT IOL = 3.0 mA. See note 1. — — VSS + 0.4 V CMOS HIGH-level input voltage VIHC See note 2. 0.8 VDD —VDD V LOW-level input voltage VILC See note 2. VSS — 0.2 VDD V HIGH-level output voltage VOHC IOH = –2.0 mA. See note 2. VDD – 0.4 — — V LOW-level output voltage VOLC IOH = 1.6 mA. See note 2. — — VSS + 0.4 V Open-drain LOW-level output voltage VOLN IOL = 6.0 mA. — — VSS + 0.4 V Schmitt-trigger Rising-edge threshold voltage VT+ See note 3. 0.5 VDD 0.7 VDD 0.8 VDD V Falling-edge threshold voltage VT– See note 3. 0.2 VDD 0.3 VDD 0.5 VDD V SPECIFICATIONS |
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