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S1D13706F00A Datasheet(PDF) 66 Page - Epson Company |
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S1D13706F00A Datasheet(HTML) 66 Page - Epson Company |
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66 / 94 page  60 EPSON S1D13305 Series Technical Manual Figure 47. Display memory write cycle Figure 48. Display memory read cycle Note A possible problem with the display memory read cycle is that the system bus access time, tACC, does not depend on the display memory access time, tACV. The microprocessor may only make repeated reads if the read loop time exceeds the S1D13305 series cycle time, tCYC. If it does not, NOP instructions may be inserted in the program loop. tACC, tACV and tCYC limits are given in section 6.2. WR D0 to D7 VR/W VD0 to VD7 tCYC Command write Data write Data write Microprocessor Display memory VRW tCYC Command write Data read Data read WR RD D0 to D7 VR/W VD0 to VD7 Microprocessor Display memory VRW MICROPROCESSOR INTERFACE |
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