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M58WR016QT Datasheet(PDF) 91 Page - Numonyx B.V |
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M58WR016QT Datasheet(HTML) 91 Page - Numonyx B.V |
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91 / 110 page  M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB Common Flash Interface 91/110 Table 42. Bank and erase block region 2 information(1) TOP DEVICES BOTTOM DEVICES Description Offset Data Offset Data (P+28)h = 61h 01h (P+30)h = 69h 03h(2) Number of identical banks within bank region 2 07h(3) (P+29)h = 62h 00h (P+31)h = 6Ah 00h (P+2A)h = 63h 11h (P+32)h = 6Bh 11h Number of program or erase operations allowed in bank region 2: Bits 0-3: Number of simultaneous program operations Bits 4-7: Number of simultaneous erase operations (P+2B)h = 64h 00h (P+33)h = 6Ch 00h Number of program or erase operations allowed in other banks while a bank in this region is programming Bits 0-3: Number of simultaneous program operations Bits 4-7: Number of simultaneous erase operations (P+2C)h = 65h 00h (P+34)h = 6Dh 00h Number of program or erase operations allowed in other banks while a bank in this region is erasing Bits 0-3: Number of simultaneous program operations Bits 4-7: Number of simultaneous erase operations (P+2D)h = 66h 02h (P+35)h = 6Eh 01h Types of erase block regions in Bank region 2 n = number of erase block regions with contiguous same-size erase blocks. Symmetrically blocked banks have one blocking region.(4) (P+2E)h = 67h 06h (P+36)h = 6Fh 07h Bank Region 2 Erase Block Type 1 Information Bits 0-15: n+1 = number of identical-sized erase blocks in each bank Bits 16-31: n×256 = number of bytes in erase block region (P+2F)h = 68h 00h (P+37)h = 70h 00h (P+30)h = 69h 00h (P+38)h = 71h 00h (P+31)h = 6Ah 01h (P+39)h = 72h 01h (P+32)h = 6Bh 64h (P+3A)h = 73h 64h Bank Region 2 (Erase Block Type 1) Minimum block erase cycles × 1000 (P+33)h = 6Ch 00h (P+3B)h = 74h 00h (P+34)h = 6Dh 01h (P+3C)h = 75h 01h Bank Region 2 (Erase Block Type 1): BIts per cell, internal ECC Bits 0-3: bits per cell in erase region Bit 4: reserved for “internal ECC used” BIts 5-7: reserved |
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