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M58WR016QT Datasheet(PDF) 48 Page - Numonyx B.V

Part # M58WR016QT
Description  16 Mbit and 32 Mbit (x16, Multiple Bank, Burst) 1.8V supply Flash memories
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Manufacturer  NUMONYX [Numonyx B.V]
Direct Link  http://www.numonyx.com
Logo NUMONYX - Numonyx B.V

M58WR016QT Datasheet(HTML) 48 Page - Numonyx B.V

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Read modes
M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB
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9.2.1
Synchronous Burst Read Suspend
A Synchronous Burst Read operation can be suspended, freeing the data bus for other
higher priority devices. It can be suspended during the initial access latency time (before
data is output) in which case the initial latency time can be reduced to zero, or after the
device has output data. When the Synchronous Burst Read operation is suspended, internal
array sensing continues and any previously latched internal data is retained. A burst
sequence can be suspended and resumed as often as required as long as the operating
conditions of the device are met.
A Synchronous Burst Read operation is suspended when E is low and the current address
has been latched (on a Latch Enable rising edge or on a valid clock edge). The clock signal
is then halted at VIH or at VIL, and G goes high.
When G becomes low again and the clock signal restarts, the Synchronous Burst Read
operation is resumed exactly where it stopped.
WAIT being gated by E remains active and will not revert to high-impedance when G goes
high. So if two or more devices are connected to the system’s READY signal, to prevent bus
contention the WAIT signal of the Flash memory should not be directly connected to the
system’s READY signal.
See Table 22: Synchronous Read AC characteristics and Figure 14: Synchronous Burst
Read Suspend AC waveforms, for details.
9.3
Single Synchronous Read mode
Single Synchronous Read operations are similar to Synchronous Burst Read operations
except that only the first data output after the X latency is valid. Synchronous Single Reads
are used to read the Electronic Signature, Status Register, CFI, Block Protection Status,
Configuration Register Status or Protection Register. When the addressed bank is in Read
CFI, Read Status Register or Read Electronic Signature mode, the WAIT signal is always
asserted.
See Table 22: Synchronous Read AC characteristics and Figure 13: Single Synchronous
Read AC waveforms, for details.


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