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M58WR016QT Datasheet(PDF) 44 Page - Numonyx B.V |
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M58WR016QT Datasheet(HTML) 44 Page - Numonyx B.V |
44 / 110 page ![]() Configuration Register M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB 44/110 Figure 6. X-Latency and data output configuration example 0 0-1-2-3 0-1-2-3-4-5- 6-7 0-1-2-3-4-5-6-7-8-9- 10-11-12-13-14-15 Same as for Wrap (Wrap /No Wrap has no effect on Continuous Burst) 1 1-2-3-4 1-2-3-4-5-6- 7-8 1-2-3-4-5-6-7-8-9- 10-11-12-13-14-15- WAIT-16 2 2-3-4-5 2-3-4-5-6-7- 8-9... 2-3-4-5-6-7-8-9-10- 11-12-13-14-15- WAIT-WAIT-16-17 3 3-4-5-6 3-4-5-6-7-8- 9-10 3-4-5-6-7-8-9-10- 11-12-13-14-15- WAIT-WAIT-WAIT- 16-17-18 ... 7 7-8-9-10 7-8-9-10-11- 12-13-14 7-8-9-10-11-12-13- 14-15-WAIT-WAIT- WAIT-16-17-18-19- 20-21-22 ... 12 12-13-14- 15 12-13-14- 15-16-17- 18-19 12-13-14-15-16-17- 18-19-20-21-22-23- 24-25-26-27 13 13-14-15- WAIT-16 13-14-15- WAIT-16-17- 18-19-20 13-14-15-WAIT-16- 17-18-19-20-21-22- 23-24-25-26-27-28 14 14-15- WAIT- WAIT-16- 17 14-15-WAIT- WAIT-16-17- 18-19-20-21 14-15-WAIT-WAIT- 16-17-18-19-20-21- 22-23-24-25-26-27- 28-29 15 15-WAIT- WAIT- WAIT-16- 17-18 15-WAIT- WAIT-WAIT- 16-17-18- 19-20-21-22 15-WAIT-WAIT- WAIT-16-17-18-19- 20-21-22-23-24-25- 26-27-28-29-30 Table 11. Burst type definition (continued) Start Add 4 Words 8 Words 16 Words Continuous Burst Sequential Interleaved Sequential Interleaved Sequential Interleaved AI10174 Amax-A0 VALID ADDRESS K L DQ15-DQ0 VALID DATA X-latency VALID DATA tACC tAVK_CPU tK tQVK_CPU tQVK_CPU tKQV 1st cycle 2nd cycle 3rd cycle 4th cycle Notes: 1. Settings shown: X-latency = 4, Data Output held for one clock cycle. 2. Amax is equal to A19 in the M58WR016QT/B and to A20 in the M58WR032QT/B. E tDELAY |
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