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M58WR016QT Datasheet(PDF) 39 Page - Numonyx B.V |
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M58WR016QT Datasheet(HTML) 39 Page - Numonyx B.V |
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39 / 110 page  M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB Configuration Register 39/110 8 Configuration Register The Configuration Register is used to configure the type of bus access that the memory will perform. Refer to Read Modes section for details on read operations. The Configuration Register is set through the Command Interface. After a Reset or Power- Up the device is configured for asynchronous page read (CR15 = 1). The Configuration Register bits are described in Table 10. They specify the selection of the burst length, burst type, burst X latency and the Read operation. Refer to Figures 6 and 7 for examples of synchronous burst configurations. 8.1 Read Select Bit (CR15) The Read Select bit, CR15, is used to switch between asynchronous and synchronous Bus Read operations. When the Read Select bit is set to ’1’, read operations are asynchronous; when the Read Select bit is set to ’0’, read operations are synchronous. Synchronous Burst Read is supported in both parameter and main blocks and can be performed across banks. On reset or power-up the Read Select bit is set to’1’ for asynchronous access. 8.2 X-Latency Bits (CR13-CR11) The X-Latency bits are used during Synchronous Read operations to set the number of clock cycles between the address being latched and the first data becoming available. For correct operation the X-Latency bits can only assume the values in Table 10: Configuration Register bits. The correspondence between X-Latency settings and the maximum sustainable frequency must be calculated taking into account some system parameters. Two conditions must be satisfied: 1. Depending on whether tAVK_CPU or tDELAY is supplied either one of the following two equations must be satisfied: (n + 1) tK ≥ tACC - tAVK_CPU + tQVK_CPU (n + 2) tK ≥ tACC + tDELAY + tQVK_CPU 2. and also tK > tKQV + tQVK_CPU where: ● n is the chosen X-Latency configuration code ● tK is the clock period ● tAVK_CPU is clock to address valid, L Low, or E Low, whichever occurs last ● tDELAY is address valid, L Low, or E Low to clock, whichever occurs last ● tQVK_CPU is the data setup time required by the system CPU, ● tKQV is the clock to data valid time ● tACC is the random access time of the device. Refer to Figure 6: X-Latency and data output configuration example. |
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