M58WR064HU datasheet(4/114 Pages) NUMONYX

Part #	M58WR064HU

Description	64 Mbit (4Mb x16, Mux I/O, Multiple Bank, Burst) 1.8V supply Flash memories

Download	114 Pages

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Manufacturer	NUMONYX [Numonyx B.V]

Direct Link	http://www.numonyx.com

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4 / 114 page

Contents

M58WR064HU M58WR064HL

4/114

7.0.6

Program Suspend Status Bit (SR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

7.0.7

Block Protection Status Bit (SR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

7.0.8

Bank Write/Multiple Word Program Status Bit (SR0) . . . . . . . . . . . . . . . 37

8

Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

8.1

Read Select Bit (CR15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

8.2

Bus Invert Configuration (CR14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

8.3

X-Latency Bits (CR13-CR11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

8.4

Wait Polarity Bit (CR10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

8.5

Data Output Configuration Bit (CR9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

8.6

Wait Configuration Bit (CR8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

8.7

Burst Type Bit (CR7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

8.8

Valid Clock Edge Bit (CR6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

8.9

Power-Down Bit (CR5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

8.10

Wrap Burst Bit (CR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

8.11

Burst length Bits (CR2-CR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

9

Read modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

9.1

Asynchronous Read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

9.2

Synchronous Burst Read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

9.2.1

Synchronous Burst Read Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

9.3

Single Synchronous Read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

10

Dual operations and multiple bank architecture . . . . . . . . . . . . . . . . . 50

11

Block locking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

11.1

Reading a block’s lock status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

11.2

Locked state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

11.3

Unlocked state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

11.4

Lock-Down state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

11.5

Locking operations during Erase Suspend . . . . . . . . . . . . . . . . . . . . . . . . 53

12

Program and erase times and endurance cycles . . . . . . . . . . . . . . . . . 55

13

Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

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