M58WR064HT datasheet(32/111 Pages) NUMONYX

Part #	M58WR064HT

Description	64 Mbit (4Mb x16, Multiple Bank, Burst) 1.8V supply Flash memories

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Manufacturer	NUMONYX [Numonyx B.V]

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Command interface - Factory program commands

M58WR064HT, M58WR064HB

32/111

6.11

Load Phase

The Load Phase requires 4 cycles to load the data (refer to Table 7: Factory Program

Commands and Figure 28: Quadruple Enhanced Factory Program Flowchart). Once the

first Word of each Page is written it is impossible to exit the Load phase until all four Words

have been written.

Two successive steps are required to issue and execute the Load Phase of the Quadruple

Enhanced Factory Program command.

1.

Use one Bus Write operation to latch the Start Address and the first Word of the first

Page to be programmed, where the start address is the location of the first data to be

programmed. For subsequent Pages the first Word address can remain the Start

Address (in which case the next Page is programmed) or can be any address in the

same block. If any address with data FFFFh is given that is not in the same block as the

Start Address, the device enters the Exit Phase. For the first Load Phase Status

Register bit SR7 should be read after the first Word has been issued to check that the

command has been accepted (bit SR7 set to ‘0’). This check is not required for

subsequent Load Phases.

2.

Each subsequent Word to be programmed is latched with a new Bus Write operation.

The address is only checked for the first Word of each Page as the order of the Words

to be programmed is fixed.

The memory is now set to enter the Program and Verify Phase.

6.12

Program and Verify Phase

In the Program and Verify Phase the four Words that were loaded in the Load Phase are

programmed in the memory array and then verified by the Program/Erase Controller. If any

errors are found the Program/Erase Controller reprograms the location. During this phase

the Status Register shows that the Program/Erase Controller is busy, Status Register bit

SR7 set to ‘0’, and that the device is not waiting for new data, Status Register bit SR0 set to

‘1’. When Status Register bit SR0 is set to ‘0’ the Program and Verify phase has terminated.

Once the Verify Phase has successfully completed subsequent pages in the same block can

be loaded and programmed. The device returns to the beginning of the Load Phase by

issuing one Bus Write operation to latch the Address and the first of the four new Words to

be programmed.

6.13

Exit Phase

Finally, after all the pages have been programmed, write one Bus Write operation with data

FFFFh to any address outside the block containing the Start Address, to terminate the Load

and Program and Verify Phases.

Status Register bit SR7 set to ‘1’ and bit SR0 set to ‘0’ indicate that the Quadruple

Enhanced Factory Program command has terminated. A full Status Register check should

be done to ensure that the block has been successfully programmed. See the section on the

Status Register for more details.

If the Program and Verify Phase has successfully completed the memory returns to Read

mode. If the P/E.C. fails to program and reprogram a given location, the error will be

signaled in the Status Register.

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