Summary description

M36L0T7050T2, M36L0T7050B2

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Summary description

The M36L0T7050T2 and M36L0T7050B2 combine two memory devices in a Multi-Chip

Package:

●

a 128-Mbit, Multiple Bank, Multi-Level, Burst, Flash memory, the M58LT128HT or

M58LT128HB

●

a 32-Mbit PseudoSRAM, the M69KW048BD.

The purpose of this document is to describe how the two memory components operate with

respect to each other. It should be read in conjunction with the M58LT128HTB and

M69KW048BD datasheets, where all specifications required to operate the Flash memory

and PSRAM components are fully detailed. These datasheets are available from your local

Numonyx distributor.

Recommended operating conditions do not allow more than one memory to be active at the

same time.

The memory is offered in a Stacked TFBGA88 (8 x 10mm, 8x10 ball array, 0.8mm pitch)

package. The devices are supplied with all the bits erased (set to ‘1’).

Figure 1.

Logic diagram

AI12878

23

A0-A22

DQ0-DQ15

M36L0T7050T2

M36L0T7050B2

16

VSS