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M29DW641F Datasheet(PDF) 16 Page - Numonyx B.V

Part # M29DW641F
Description  64 Mbit (4Mb x16, Multiple Bank, Page, Boot Block) 3V Supply Flash Memory
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Manufacturer  NUMONYX [Numonyx B.V]
Direct Link  http://www.numonyx.com
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M29DW641F Datasheet(HTML) 16 Page - Numonyx B.V

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Bus Operations
M29DW641F
16/80
3
Bus Operations
There are five standard Bus Operations that control the device. These are Bus Read
(Random and Page modes), Bus Write, Output Disable, Standby and Automatic Standby.
Dual Operations are possible in the M29DW641F, thanks to their multiple bank architecture.
While programming or erasing in one banks, Read Operations are possible in any of the
other banks. Write Operations are only allowed in one bank at a time.
See
Table 3: Bus Operations, for a summary. Typically glitches of less than 5ns on Chip
Enable, Write Enable, and Reset/Block Temporary Unprotect pins are ignored by the
memory and do not affect Bus Operations.
3.1
Bus Read
Bus Read Operations read from the memory cells, or specific registers in the Command
Interface. To speed up the Read Operation the memory array can be read in Page mode
where data is internally read and stored in a page buffer. The Page has a size of 8 Words
and is addressed by the address inputs A0-A2.
A valid Bus Read Operation involves setting the desired address on the Address Inputs,
applying a Low signal, VIL, to Chip Enable and Output Enable and keeping Write Enable
High, VIH. The Data Inputs/Outputs will output the value, see Figure 11: Random Read AC
waveforms, Figure 12: Page Read AC waveforms, and Table 20: Read AC characteristics,
for details of when the output becomes valid.
3.2
Bus Write
Bus Write Operations write to the Command Interface. A valid Bus Write Operation begins
by setting the desired address on the Address Inputs. The Address Inputs are latched by the
Command Interface on the falling edge of Chip Enable or Write Enable, whichever occurs
last. The Data Inputs/Outputs are latched by the Command Interface on the rising edge of
Chip Enable or Write Enable, whichever occurs first. Output Enable must remain High, VIH,
during the whole Bus Write Operation. See
Figure 13 and Figure 14, Write AC Waveforms,
and
Table 21 and Table 22, Write AC Characteristics, for details of the timing requirements.
3.3
Output Disable
The Data Inputs/Outputs are in the high impedance state when Output Enable is High, VIH.
3.4
Standby
When Chip Enable is High, VIH, the memory enters Standby mode and the Data
Inputs/Outputs pins are placed in the high-impedance state. To reduce the Supply current to
the Standby Supply current, ICC2, Chip Enable should be held within VCC ± 0.2V. For the
Standby current level see
Table 19: DC characteristics.
During program or Erase Operations the memory will continue to use the Program/Erase
Supply current, ICC3, for Program or Erase Operations until the operation completes.


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