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M29DW641F Datasheet(PDF) 13 Page - Numonyx B.V |
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M29DW641F Datasheet(HTML) 13 Page - Numonyx B.V |
13 / 80 page M29DW641F Signal descriptions 13/80 2 Signal descriptions See Figure 1: Logic diagram, and Table 1: Signal names, for a brief overview of the signals connected to this device. 2.1 Address Inputs (A0-A21) The Address Inputs select the cells in the memory array to access during Bus Read Operations. During Bus Write Operations they control the commands sent to the Command Interface of the internal state machine. 2.2 Data Inputs/Outputs (DQ0-DQ15) The Data I/O output the data stored at the selected address during a Bus Read Operation. During Bus Write Operations they represent the commands sent to the Command Interface of the Program/Erase Controller. 2.3 Chip Enable (E) The Chip Enable, E, activates the memory, allowing Bus Read and Bus Write Operations to be performed. When Chip Enable is High, VIH, all other pins are ignored. 2.4 Output Enable (G) The Output Enable, G, controls the Bus Read Operation of the memory. 2.5 Write Enable (W) The Write Enable, W, controls the Bus Write Operation of the memory’s Command Interface. 2.6 VPP/Write Protect (VPP/WP) The VPP/Write Protect pin is both a power supply and a write protect pin. When VPP/Write Protect is Low, VIL, it is seen as a write protect pin protecting the four outermost parameter blocks (two at the top, and two at the bottom of the address space). Program and erase Operations in these blocks are ignored while VPP/Write Protect is Low, even when RP is at VID. When VPP/Write Protect is High, VIH, the memory reverts to the previous protection state of the four outermost parameter blocks. Program and Erase Operations can now modify the data in these blocks unless the blocks are protected using Block Protection. Applying VPPH to the VPP/WP pin will temporarily unprotect any block previously protected (including the four outermost parameter blocks) using a High voltage Block Protection |
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