M29DW128F datasheet(14/94 Pages) NUMONYX

Part #	M29DW128F

Description	128 Mbit (16Mb x8 or 8Mb x16, Multiple Bank, Page, Boot Block) 3V supply Flash memory

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Manufacturer	NUMONYX [Numonyx B.V]

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Signal descriptions

M29DW128F

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2

Signal descriptions

See

Figure 1: Logic diagram, and Table 1: Signal names, for a brief overview of the signals

connected to this device.

2.1

Address Inputs (A0-A22)

The Address Inputs select the cells in the memory array to access during Bus Read

operations. During Bus Write operations they control the commands sent to the Command

Interface of the Program/Erase Controller.

2.2

Data Inputs/Outputs (DQ0-DQ7)

The Data I/O outputs the data stored at the selected address during a Bus Read operation.

During Bus Write operations they represent the commands sent to the Command Interface

of the internal state machine.

2.3

Data Inputs/Outputs (DQ8-DQ14)

The Data I/O outputs the data stored at the selected address during a Bus Read operation

when BYTE is High, VIH. When BYTE is Low, VIL, these pins are not used and are high

impedance. During Bus Write operations the Command Register does not use these bits.

When reading the Status Register these bits should be ignored.

2.4

Data Input/Output or Address Input (DQ15A–1)

When the device is in x16 Bus mode, this pin behaves as a Data Input/Output pin (as DQ8-

DQ14). When the device is in x8 Bus mode, this pin behaves as an address pin; DQ15A–1

Low will select the LSB of the addressed Word, DQ15A–1 High will select the MSB.

Throughout the text consider references to the Data Input/Output to include this pin when

the device operates in x16 bus mode and references to the Address Inputs to include this

pin when the device operates in x8 bus mode except when stated explicitly otherwise.

2.5

Chip Enable (E)

The Chip Enable pin, E, activates the memory, allowing Bus Read and Bus Write operations

to be performed. When Chip Enable is High, VIH, all other pins are ignored.

2.6

Output Enable (G)

The Output Enable pin, G, controls the Bus Read operation of the memory.

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