M29DW128F datasheet(49/94 Pages) NUMONYX

Part #	M29DW128F

Description	128 Mbit (16Mb x8 or 8Mb x16, Multiple Bank, Page, Boot Block) 3V supply Flash memory

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Manufacturer	NUMONYX [Numonyx B.V]

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M29DW128F

Status Register

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7

Status Register

The M29DW128F has one Status Register. The Status Register provides information on the

current or previous Program or Erase operations executed in each bank. The various bits

convey information and errors on the operation. Bus Read operations from any address

within the Bank, always read the Status Register during Program and Erase operations. It is

also read during Erase Suspend when an address within a block being erased is accessed.

The bits in the Status Register are summarized in

Table 19: Status Register bits.

7.1

Data Polling bit (DQ7)

The Data Polling bit can be used to identify whether the Program/Erase Controller has

successfully completed its operation or if it has responded to an Erase Suspend. The Data

Polling bit is output on DQ7 when the Status Register is read.

During Program operations the Data Polling bit outputs the complement of the bit being

programmed to DQ7. After successful completion of the Program operation the memory

returns to Read mode and Bus Read operations from the address just programmed output

DQ7, not its complement.

During Erase operations the Data Polling bit outputs ’0’, the complement of the erased state

of DQ7. After successful completion of the Erase operation the memory returns to Read

mode.

In Erase Suspend mode the Data Polling bit will output a ’1’ during a Bus Read operation

within a block being erased. The Data Polling bit will change from a ’0’ to a ’1’ when the

Program/Erase Controller has suspended the Erase operation.

Figure 8: Data Polling flowchart, gives an example of how to use the Data Polling bit. A Valid

Address is the address being programmed or an address within the block being erased.

7.2

Toggle bit (DQ6)

The Toggle bit can be used to identify whether the Program/Erase Controller has

successfully completed its operation or if it has responded to an Erase Suspend. The Toggle

bit is output on DQ6 when the Status Register is read.

During a Program/Erase operation the Toggle bit changes from ’0’ to ’1’ to ’0’, etc., with

successive Bus Read operations at any address. After successful completion of the

operation the memory returns to Read mode.

During Erase Suspend mode the Toggle bit will output when addressing a cell within a block

being erased. The Toggle bit will stop toggling when the Program/Erase Controller has

suspended the Erase operation.

Figure 9: Toggle flowchart, gives an example of how to use the Data Toggle bit. Figure 16

and

Figure 17 describe Toggle bit timing waveform.

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