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M28W320FCT Datasheet(PDF) 19 Page - Numonyx B.V |
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M28W320FCT Datasheet(HTML) 19 Page - Numonyx B.V |
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19 / 69 page  M28W320FCT, M28W320FCB Command interface 19/69 4.7 Double Word Program command This feature is offered to improve the programming throughput, writing a page of two adjacent words in parallel.The two words must differ only for the address A0. Programming should not be attempted when VPP is not at VPPH. Three bus write cycles are necessary to issue the Double Word Program command. 1. The first bus cycle sets up the Double Word Program Command. 2. The second bus cycle latches the Address and the Data of the first word to be written. 3. The third bus cycle latches the Address and the Data of the second word to be written and starts the Program/Erase Controller. Read operations output the Status Register content after the programming has started. Programming aborts if Reset goes to VIL. As data integrity cannot be guaranteed when the program operation is aborted, the block containing the memory location must be erased and reprogrammed. See Appendix C, Figure 17: Double Word Program Flowchart and Pseudo Code, for the flowchart for using the Double Word Program command. 4.8 Quadruple Word Program command This feature is offered to improve the programming throughput, writing a page of four adjacent words in parallel.The four words must differ only for the addresses A0 and A1. Programming should not be attempted when VPP is not at VPPH. Five bus write cycles are necessary to issue the Quadruple Word Program command. 1. The first bus cycle sets up the Quadruple Word Program Command. 2. The second bus cycle latches the Address and the Data of the first word to be written. 3. The third bus cycle latches the Address and the Data of the second word to be written. 4. The fourth bus cycle latches the Address and the Data of the third word to be written. 5. The fifth bus cycle latches the Address and the Data of the fourth word to be written and starts the Program/Erase Controller. Read operations output the Status Register content after the programming has started. Programming aborts if Reset goes to VIL. As data integrity cannot be guaranteed when the program operation is aborted, the block containing the memory location must be erased and reprogrammed. See Appendix C, Figure 18: Quadruple Word Program Flowchart and Pseudo Code, for the flowchart for using the Quadruple Word Program command. 4.9 Clear Status Register command The Clear Status Register command can be used to reset bits 1, 3, 4 and 5 in the Status Register to ‘0’. One bus write cycle is required to issue the Clear Status Register command. The bits in the Status Register do not automatically return to ‘0’ when a new Program or Erase command is issued. The error bits in the Status Register should be cleared before attempting a new Program or Erase command. |
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