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M28W160CT Datasheet(PDF) 10 Page - Numonyx B.V |
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M28W160CT Datasheet(HTML) 10 Page - Numonyx B.V |
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10 / 50 page  M28W160CT, M28W160CB 10/50 BUS OPERATIONS There are six standard bus operations that control the device. These are Bus Read, Bus Write, Out- put Disable, Standby, Automatic Standby and Re- set. See Table 3, Bus Operations, for a summary. Typically glitches of less than 5ns on Chip Enable or Write Enable are ignored by the memory and do not affect bus operations. Read. Read Bus operations are used to output the contents of the Memory Array, the Electronic Signature, the Status Register and the Common Flash Interface. Both Chip Enable and Output En- able must be at VIL in order to perform a read op- eration. The Chip Enable input should be used to enable the device. Output Enable should be used to gate data onto the output. The data read de- pends on the previous command written to the memory (see Command Interface section). See Figure 9, Read Mode AC Waveforms, and Table 16, Read AC Characteristics, for details of when the output becomes valid. Read mode is the default state of the device when exiting Reset or after power-up. Write. Bus Write operations write Commands to the memory or latch Input Data to be programmed. A write operation is initiated when Chip Enable and Write Enable are at VIL with Output Enable at VIH. Commands, Input Data and Addresses are latched on the rising edge of Write Enable or Chip Enable, whichever occurs first. See Figures 10 and 11, Write AC Waveforms, and Tables 17 and 18, Write AC Characteristics, for details of the timing requirements. Output Disable. The data outputs are high im- pedance when the Output Enable is at VIH. Standby. Standby disables most of the internal circuitry allowing a substantial reduction of the cur- rent consumption. The memory is in stand-by when Chip Enable is at VIH and the device is in read mode. The power consumption is reduced to the stand-by level and the outputs are set to high impedance, independently from the Output Enable or Write Enable inputs. If Chip Enable switches to VIH during a program or erase operation, the de- vice enters Standby mode when finished. Automatic Standby. Automatic Standby pro- vides a low power consumption state during Read mode. Following a read operation, the device en- ters Automatic Standby after 150ns of bus inactiv- ity even if Chip Enable is Low, VIL, and the supply current is reduced to IDD1. The data Inputs/Out- puts will still output data if a bus Read operation is in progress. Reset. During Reset mode when Output Enable is Low, VIL, the memory is deselected and the out- puts are high impedance. The memory is in Reset mode when Reset is at VIL. The power consump- tion is reduced to the Standby level, independently from the Chip Enable, Output Enable or Write En- able inputs. If Reset is pulled to VSS during a Pro- gram or Erase, this operation is aborted and the memory content is no longer valid. Table 3. Bus Operations Note: X = VIL or VIH, VPPH = 12V ± 5%. Operation E G W RP WP VPP DQ0-DQ15 Bus Read VIL VIL VIH VIH X Don't Care Data Output Bus Write VIL VIH VIL VIH X VDD or VPPH Data Input Output Disable VIL VIH VIH VIH X Don't Care Hi-Z Standby VIH XX VIH X Don't Care Hi-Z Reset XXX VIL X Don't Care Hi-Z |
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