CONFIDENTIAL
PRELIMINARY
CYNSE10512
CYNSE10256
CYNSE10128
Document #: 38-02069 Rev. *F
Page 33 of 153
5.4.10
Hardware Register (HARDWARE)
The Hardware register controls the drive strength of the groups of signals as listed in Section 6.0. Table 5-11 shows the fields
that control each of the group and the output signals associated with it.
Table 5-11. Hardware Register Description
Field
Range
(decimal)
Initial Value
(binary)
Description
[1:0]
Reserved.
IOJTAG
[3:2]
11
JTAG I/Os. Sets the drive strength for the I/O. By default it is set to “11”. The
following output signal is part of this group: TDO.
The LVCMOS I/O drive strength for encoding is as listed below:
00: 2 mA
01: 8 mA
10: 16 mA
11: 24 mA (VDDQ = 2.5V); 20 mA (VDDQ = 1.8V)
The HSTL I/O drive strength for encoding is as listed below:
00: 8 mA (HSTL I)
01: Reserved
10: Reserved
11: 17 mA (HSTL II)
IOCAS
[5:4]
11
Cascade I/Os. The following output signals are part of this group:
LHO, BHO and FULO.
Refer to IOJTAG above for I/O drive strength encoding.
IOSRAM
[7:6]
11
SRAM I/Os. The following output signals are part of this group:
SADR, CE_L, WE_L, OE_L and ALE_L.
Refer to IOJTAG above for I/O drive strength encoding.
IODQ
[9:8]
11
Command and DQ Bus I/Os. The following output signals are part of this group:
DQ, ACK, EOT, SSF, SSV, PAR, PARERR_L, MULTI_HIT, and FULL.
Refer to IOJTAG above for I/O drive strength encoding.
[63:10]
Reserved.
[71:64]
0
Reserved. This field must be set to 0.
7
15
23
0
39
47
55
31
63
71
Figure 5-17. Hardware Register
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