CONFIDENTIAL
PRELIMINARY
CYNSE10512
CYNSE10256
CYNSE10128
Document #: 38-02069 Rev. *F
Page 28 of 153
5.4.4
Command Register (COMMAND)
Table 5-5 describes the command register fields. This register is expected to be initialized by the user right after reset before
performing any Read, Write, Learn, Search, or Parity operations and thereafter not changed during normal operation. The user
must also wait for at least 32 CLK2X cycles after a write to the COMMAND register before issuing the next command.
Table 5-4. Search Successful Register Description
Field
Range
(decimal)
Initial Value
(binary)
Description
INDEX
[N:0]
0
Index. This is the address of the 72-bit entry where a successful search occurs. This index
is updated if the device is either a local or global winner in a Search operation. N = 17 for
CYNSE10512, 16 for CYNSE10256, 15 for CYNSE10128.
If a hit occurs in a 144-bit table, the least-significant bit (LSB) is cleared to 0.
If a hit occurs in a 288-bit table, the two LSBs are cleared to 0.
If a hit occurs in a 576-bit table, the three LSBs are cleared to 0.
[29:N + 1]
Reserved.
GVAL
[30]
0
Global Valid. Valid only in Enhanced mode. It is updated when the device performs a
Search operation. It is set to 1 when there is no hit anywhere in the cascade and this device
is the last one in the cascade (LDEV field in CMD register is set to 1). Otherwise it is cleared
to 0. When set to 1, the device is responsible for responding to broadcast PIO operation.
VAL
[31]
0
Valid. This field is updated when the device performs a Search operation. It is set to 1 only
when the device is a global winner. Otherwise it will be cleared to 0.
[71:32]
Reserved.
Table 5-5. Command Register Description
Field
Range
(decimal)
Initial Value
(binary)
Description
SRST
[0]
0
Software Reset. If set to 1, this bit resets the device with the same effect as a hardware
reset. Internally, it generates a reset pulse lasting for eight CLK2X cycles. This bit automat-
ically resets to 0 after the reset pulse is deasserted.
DEVE
[1]
0
Device Enable. If 0, it keeps the SRAM bus (SADR, WE_L, CE_L, OE_L and ALE_L), SSF,
and SSV signals in a three-state condition and forces the cascade interface output signals
LHO[1:0] and BHO[2:0] to 0. It also keeps the DQ bus in input mode. The purpose is to make
sure that there are no bus contentions when the device powers up. Set this bit to 1 when the
device is ready for operation.
TLSZ
[3:2]
10
Table Size. This field increases the pipeline latency of the Search and Learn operations as
well as the Read and Write accesses to the SRAM. Once programmed, it is expected to not
be changed.
Affected signals in both Enhanced and Non-Enhanced Modes:
SADR, CE_L, OE_L, WE_L, ALE_L, SSV, SSF, and ACK.
Affected signals only in Enhanced Mode:
FULL and MULTI_HIT.
Latency in number of CLK cycles:
“00”: 4 cycles
“01”: 5 cycle
“10”: 6 cycles
“11”: Reserved/Invalid
When HIGH_SPEED1 is set to 1, “00” is not supported.
When HIGH_SPEED2 is set to 1, “00” and “01” are not supported.
7
15
23
0
39
47
55
31
63
71
CFGA
Figure 5-11. Command Register
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