CONFIDENTIAL
PRELIMINARY
CYNSE10512
CYNSE10256
CYNSE10128
Document #: 38-02069 Rev. *F
Page 26 of 153
5.4.1
Comparand Register (CMPR)
The device contains 16 pairs of comparand registers (one pair is 144 bits) dynamically selected in every Search operation to store
the comparand presented on the DQ bus. The device may later use these registers when it executes a Learn operation. Search
and Learn commands specify the comparand registers in pairs. The Ayama 10000 device stores the Search command’s cycle A
comparand in the even-numbered register and the cycle B comparand in the odd-numbered register, as shown in Figure 5-8. For
wider width keys, pairs of comparand registers are concatenated together. The concatenation of the registers must be done by
the user. On a 72-bit operation, both halves of the comparand register must be loaded with the same value. When performing
MultiSearch operation, the NSE requires two comparand registers for an operation. The first comparand register is specified in
the command and the NSE automatically selects the comparand register one index higher than the command specified register.
When the device powers-up, the CMPR registers are initialized to 0.
5.4.2
Global Mask Register (GMR)
The device contains 16 pairs of GMRs (one pair is 144 bits) dynamically selected in every Search operation to select the Search
subfield. The addressing of these registers is shown in Figure 5-9. The GMR index supplied on the command bus selects one of
the sixteen pairs of global masks during Search and Write operations. In 72-bit Search and Write operations, the host ASIC must
program both the even and odd mask registers with the same values. For a MultiSearch operation, two separate GMRs are used
in the operation. The first one is specified in the command and the second one is one index higher.
Each mask bit in the GMRs is used during Search and Write operations. In a Search operation, setting the mask bit to 1 enables
while setting the mask bit to 0 disables compares at the corresponding bit position (forced match). In Write operations to the data
or mask array, setting the mask bit to 1 enables Write while setting the mask bit to 0 disables Write at the corresponding bit
position. Write operation to internal registers does not use the GMR to mask the data and ignores the GMR selection when the
command is issued.
When the device powers-up, the GMR registers are initialized to 0. Figure 5-9 below shows each portion (Even, Odd) of each
GMR, and what address (in binary) is required to access that register.
112–1023
–
–
Reserved.
1024
BMRx
R/W
Block Mini-Key Register. This register holds the four Mini-Keys associated with
a block. There is one BMR per block. See Section 5.4.14.
1025
BPRx
R/W
Block Priority Register. This register holds the four sub-block priorities. There is
one BPR per block. See Section 5.4.15.
1026
BPARx
R/W
Block Parity Register. This register contains the control and status bits for
controlling and detecting parity errors for a block. There is one BPAR per block.
See Section 5.4.16.
1027
BNFAx
R
Block Next-free Address Register. This register contains the next-free entry
information for the block that it is associated with. There is one BNFA per block.
See Section 5.4.17.
1028–1031
BPRA0x–
BPRA3x
R/W
Block Priority Register Aliases. These locations are aliases for the corre-
sponding BPRx. See Section 5.4.18.
Table 5-3. List of Internal Registers (continued)
Address
(decimal)
Abbreviation
Type
(Read/Write)
Description
143
0
72
72
1
0
3
2
5
4
7
6
30
31
index
0
15
1
Address
Figure 5-8. Comparand Register Selection During Search and Learn Instructions
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