CONFIDENTIAL
PRELIMINARY
CYNSE10512
CYNSE10256
CYNSE10128
Document #: 38-02069 Rev. *F
Page 25 of 153
5.3
Output Signals Default Driver/Last Device Designation (LRAM and LDEV)
When NSEs are cascaded using multiple Ayama 10000 devices, the SADR, CE_L, and WE_L (three-state signals) are all tied
together. In order to eliminate external pull-up and pull-downs, one device in a bank is designated the default driver. For non-
search or non-learn cycles (see Subsection 6.6, “Learn Command”) or Search cycles with a global miss, the SADR, CE_L, and
WE_L signals are driven by the device with the LRAM bit set. It is important that only one device in a bank of cascaded NSEs
have this bit set. Failure to do so will cause contention on the SADR, CE_L, and WE_L, and can potentially cause damage to the
device(s).
Similarly, when NSEs using multiple Ayama 10000 devices are cascaded, SSF and SSV (also three-state signals) are tied
together. In order to eliminate external pull-up and pull-downs, one device in a bank is designated as the default driver. For non-
search cycles or Search cycles with a global miss, the SSF and SSV signals are driven by the device with the LDEV bit set. It is
important that only one device in a bank of cascaded NSEs have this bit set. Failure to do so will cause contention on the SSV
and SSF, and can potentially cause damage to the device(s).
5.4
Registers
Table 5-3 provides an overview of all the Ayama 10000 internal registers. Each register is 72 bits wide. The Ayama 10000 contains
sixteen pairs of comparand storage registers, sixteen pairs of global mask registers, eight Search status index registers, sixteen
Search control parameters registers, sixteen Search result registers and one each of command, information, burst Read, burst
Write, next-free address register, partition configuration, hardware and parity control registers. Each of the blocks in the NSE
device (128/64/32 2Kx72 blocks in CYNSE10512/256/128 respectively) also has one each of Block Mini-Key, Block Priority, Block
Parity and Block Next-free Address registers. There are also four Block Priority Register Aliases registers for each Block Priority
register that allows an alternative way to update the Block Priority registers. The registers are presented in ascending address
order. Each register group is then described in the following subsections. Reserved fields in the registers are read as 0s. When
writing to the registers, all Reserved fields must be written with 0s, unless specified otherwise in the field’s description.
Table 5-3. List of Internal Registers
Address
(decimal)
Abbreviation
Type
(Read/Write)
Description
0–31
CMPR0–15
R
Comparand Register. Sixteen CMPR pairs (144 bits per pair) that store
comparands from the DQ bus during a Search operation for later use with the Learn
command. See Section 5.4.1.
32–47
96–111
GMR0–7
GMR8–15
R/W
Global Mask Register. Sixteen GMR pairs (144 bits per pair) used for global mask
bits on the DQ bus for all commands. See Section 5.4.2.
48–55
SSR0–7
R
Search Successful Register. These registers store the result of Search opera-
tions. See Section 5.4.3.
56
COMMAND
R/W
Command Register. This register contains control fields that determine how the
NSE operates. See Section 5.4.4.
57
INFO
R
Information Register. This Read-only register contains static information about
the NSE device. See Section 5.4.5.
58
RBURREG
R/W
Burst-Read Register. This register contains the starting address and count for a
Read Burst operation. See Section 5.4.6.
59
WBURREG
R/W
Burst-Write Register. This register contains the starting address and count for a
Write Burst operation. See Section 5.4.7.
60
NFA
R
Next-free Address Register. This register contains the index of the next-free
entry when the device is in the Non-Enhanced mode (Enhanced mode uses SRR
registers to store the next-free entry information). See Section 5.4.8.
61
CONFIG
R/W
Partition Configuration Register. This register contains the partition type bits
when the NSE device operates in the Non-Enhanced mode. It is not used in the
Enhanced mode. See Section 5.4.9.
62
HARDWARE
R/W
Hardware Register. This register contains I/O drive strength settings. See
Section 5.4.10.
63
PARITY
R/W
Parity Control Register. This register contains the control and address for parity
checking of the Core and registers. See Section 5.4.11.
64–79
CPR0–15
R/W
Control Register. These registers provide Mini-Key and Soft Priority for the
associated operation. See Section 5.4.12.
80–95
SRR0–15
R
Search Result Register. These registers provide information of the next-free
entry when the device is in the Enhanced mode. (Non-Enhanced mode uses the
NFA register to store the next-free entry information.) See Section 5.4.13.
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