CONFIDENTIAL
PRELIMINARY
CYNSE10512
CYNSE10256
CYNSE10128
Document #: 38-02069 Rev. *F
Page 24 of 153
Internal register for configuration: HARDWARE.
5.2.1
ASIC Interface
The ASIC Interface includes all signals for data that comes in from and out to a system’s processing unit, which could be an
application specific (ASIC) or a more generic network processing unit (NPU and NCP). It supports LVCMOS and HSTL I/O
standards. LVCMOS allows the I/O signals to run at a rate of up to 100 MHz (CLK1X; Double data rate in MultiSearch operation).
With HSTL, the I/O signals can run at a rate of up to 133 MHz (CLK1X; Double data rate in MultiSearch operation).
The ASIC Interface includes the Command and DQ bus signal group. CMD[10:0] carries the command and its associated
parameter. DQ[71:0] is used for data transfer to and from the database entries, which are comprised of data and mask fields that
are organized as data and mask arrays. The DQ bus carries Search data (of the data and mask arrays and internal registers)
during the Search command as well as the address and data during Read and/or Write operations. The DQ bus also carries
address information for the direct accesses to the external SRAM.
5.2.2
SRAM Interface
The SRAM Interface includes output only signals that are used to interact with SRAM memory devices. As with the ASIC Interface,
it supports LVCMOS and HSTL I/O standards. LVCMOS allows the I/O signals to run at a rate of up to 100 MHz (200-MHz double
data rate with MultiSearch operation). With HSTL, the I/O signals can run at a rate of up to 133 MHz (266-MHz double date rate
with MultiSearch operation).
5.2.3
Cascade Interface
The Cascade Interface is used for cascading multiple Ayama 10000 devices in a system. It supports LVCMOS and HSTL I/O
standards that can run up to 133 MHz in all operation modes. The Cascade Interface power supply is the same power supply
that the ASIC Interface uses. Thus the selection of the I/O standard used for the Cascade Interface depends on the I/O Standard
selected for the ASIC Interface.
When multiple NSEs are cascaded to create large databases, the data being searched is presented to all NSEs in the cascaded
system simultaneously. If multiple matches occur, arbitration logic on the NSEs will enable the winning device (the one with a
matching entry closest to address 0 of the cascaded database) to drive the SRAM bus. User can set the default device to respond
to an operation when a Search operation does not result in a Search Hit. Refer to Section 5.3 for more information.
CASCADE
CASCADE
Ayama 10000
CASCADE
CASCADE
Ayama 10000
CASCADE
CASCADE
Ayama 10000
CASCADE
CASCADE
Ayama 10000
From ASIC
To SRAMs (Associative)
To ASIC (Index)
or
Figure 5-7. Ayama 10000 I/O Interfaces
[+] Feedback
[+] Feedback
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
