22 / 153 page
CONFIDENTIAL
PRELIMINARY
CYNSE10512
CYNSE10256
CYNSE10128
Document #: 38-02069 Rev. *F
Page 22 of 153
5.1.2.4 MultiSearch
When MultiSearch is activated, the Core is divided into two separate arrays. Each array is organized into 64/32/16 blocks
(corresponds to CYNSE10512/CYNSE10256/CYNSE10128, respectively) of 2K 72-bit entries. Each block can be configured to
be of width x72, x144, x288, or x576. This separation allows a Search operation to simultaneously perform the search across
both arrays. The output signals will run at double data rate to effectively increase the throughput to a maximum of 266 million
searches per second. Each array can have multiple tables with different widths. Single-Search operation outputs are driven at
the rising edge of CLK1X. When the device has the MultiSearch feature enabled and MultiSearch operation is issued (Single-
Search can still be issued even when MultiSearch is enabled), the output is driven at both rising and falling edges of CLK1X
(rising edge of CLK2X). Output from Array 0 is driven at the rising edge while output from Array 1 is driven at the falling edge of
CLK1X. Figure 5-6 shows an illustration of the MultiSearch operation.
Both arrays will use the same Search key except for search operation on 72-bit wide tables. So does the selection of the Global
Mask Register (GMR) and Comparand Register (CMPR) as listed in Table 5-2.
cycle
cycle
cycle
cycle
cycle
cycle
READ
PARITY
1
2
345
6
CLK2X
CMDV
CMD[1:0]
PARERR_L
DQ
CMD[10:2]
A
B
PHS_L
cycle
7
cycle
8
cycle
9
cycle
10
Figure 5-5. Timing Diagram of a Core Parity Error (TLSZ=00)
T
T+1
T+2
T+3
T+4
T+5
x72
x72
x576
SEARCH
Array 0
Array 1
RESULT0 RESULT1
Time
x72
x144
x288
Figure 5-6. MultiSearch Operation Overview
[+] Feedback
[+] Feedback
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
