CONFIDENTIAL
PRELIMINARY
CYNSE10512
CYNSE10256
CYNSE10128
Document #: 38-02069 Rev. *F
Page 21 of 153
Core Parity
The Core includes a one-bit parity for each 72-bit entry in the data and mask arrays. When writing into the data or mask array,
the NSE will calculate and generate the one-bit parity for each 72-bit data. Each block also has a block-associated internal register
to enable the parity checking for the block (BPAR). When disabled, the block will ignore the Read Parity command.
To issue the Read Parity command, the ASIC issues a Read command and sets the Parity field in the parameters sent through
the DQ bus as described in Table 5-25. Core parity checking is performed in parallel on four adjacent 72-bit entries per pair of
blocks. At the beginning of each parity operation, an internal address counter is incremented. The new incremented address is
then used for the parity check operation.
It will cycle through the data and mask arrays as well as odd and even blocks for both arrays for each Read Parity issued. If one
or more parity errors are detected, the error is reported in the block’s BPAR register. Then all errors are prioritized through an
arbiter to select the highest priority parity error, which is then reported in the PARITY register. PARERR_L will also be set to 0
when there is a parity error. PARERR_L is valid on the (5+TLSZ)th cycle of latency. For example, with TLSZ set to “00” and the
command is issued at Cycle1, PARERR_L will be valid on Cycle6. Read Parity also responds to broadcast CHIPID selection.
Figure 5-5 shows the timing diagram of a Core Parity error during a Read Parity instruction. The PARERR_L signal goes Low
5 cycles after the error is detected.
There are two basic flows for parity error recovery. The first flow is by reading the highest priority parity error address stored in
the PARITY register, fix the error, decrement the internal address counter and reissue Read Parity. The second flow is by reading
the PARITY register to obtain the location, reading the BPAR registers to locate blocks that has the error and then fixing those
locations.
cycle
cycle
cycle
cycle
cycle
cycle
288-bit SEARCH
1
2
345
6
CLK2X
CMDV
CMD[1:0]
PAR[0]
Even DQ
CMD[10:2]
A
B
PHS_L
cycle
7
cycle
8
cycle
9
cycle
10
A
B
Odd
bits
Odd DQ
bits
PAR[1]
Odd Odd
Even
Odd
Odd
Even
Even
PARERR_L
incorrect value for PAR[1]
TT+1
T+2
T+3
T+4
Figure 5-4. Timing Diagram of a DQ Bus Parity Error (288-bit Search, TLSZ=00)
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