CONFIDENTIAL
PRELIMINARY
CYNSE10512
CYNSE10256
CYNSE10128
Document #: 38-02069 Rev. *F
Page 20 of 153
mable Soft Priority value that becomes part of the search key when Soft Priority feature is enabled. This feature eases the
management of the tables, especially for table expansion. Each sub-block also has a Priority Valid bit that can be used to set the
Soft Priority value of the sub-block to invalid state which will also prevent the sub-block from participating in a search operation.
Figure 5-3 shows the associations of the sub-blocks and Soft Priority.
Internal registers for configuration: CMD, CPR and BPR.
5.1.2.3 Parity
Ayama 10000 introduces parity to provide additional protection for data integrity. Parity checking can be performed both on the
data transmission that passes through DQ bus and the data stored in the Core (data and mask arrays). The Parity feature can
be enabled through the PARITY register. DQ Bus and Core parity checking can be independently enabled. When parity checking
is enabled, a Write operation ignores any masking and all bits are written as presented in the DQ bus.
Even Parity is used in the parity checking. For example, if there is an odd number of logic-1 bits in a word, the corresponding
parity bit will be set High in order for the combination (word and parity bit) to have even parity.
When an error is detected, the device will update the PARITY register and set the parity error flag (PARERR_L) to report the error.
Parity status is not cascaded. However, PARERR_L is an open-drain signal to allow signals from cascaded Ayama 10000 devices
to be connected together and provide cascaded parity error detection. Therefore, the AC timing parameters associated with the
signal (rise time/fall time) will be dependent on the loading conditions. Note that all parity status fields in PARITY and BPAR
registers needs to be cleared by the ASIC after fixing the errors.
Internal registers for configuration: PARITY and BPAR.
DQ Bus Parity
The DQ bus is divided into even-bits and odd-bits groups for parity checking. Parity bits of both even- and odd-bits groups are
provided in the bidirectional PAR[1:0]. When the ASIC is driving the DQ bus, the ASIC must generate the parity bits. When the
NSE is driving the DQ bus, the NSE will generate the parity bits.
When the ASIC is driving the DQ bus, the NSE will calculate the data stream parity and compare it to PAR[1:0]. When there is
an error, the NSE will update the PARITY register and set PARERR_L to 0. PARERR_L is valid on the (3+T)th cycle of latency
for a Read operation and (4+T)th cycle of latency for the other operations. T is the cycle where the bus parity error is detected.
When a DQ bus parity error is detected, the NSE must be reset and reinitialized.
Figure 5.4 shows the timing diagram of a DQ Bus Parity error during a 288-bit Search instruction. In cycle 1B the parity of the
odd DQ bits is shown to be ‘1’ while the corresponding parity bit (PAR[1]) is ‘0’ (should be High for parity check to result in a
‘0’).The PARERR_L signal goes Low 4 cycles after the error is detected.
Block 0
Block 1
Block 2
Block N
2K x 72
512 x 72
Sub-Block 0
Sub-Block 1
Sub-Block 2
Sub-Block 3
V0
V1
V2
V3
N = 127 for CYNSE10512
63 for CYNSE10256
31 for CYNSE10128
Figure 5-3. Sub-Blocks and Soft Priority Associations
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