CONFIDENTIAL
PRELIMINARY
CYNSE10512
CYNSE10256
CYNSE10128
Document #: 38-02069 Rev. *F
Page 17 of 153
Cascade Interface (LVCMOS and HSTL)
LHI[6:0]
LHI_0[6:0] (MSE=1)
I
Local Hit In/Local Hit In Array 0. These signals are inputs from upstream devices in a
cascade that indicate whether there is a hit in the upstream/previous device(s).
When MultiSearch is performed, LHI[6:0] becomes LHI_0[6:0] (Local Hit input signals for
Array 0).
LHO[1:0]
LHO_0[1:0] (MSE=1)
O
Local Hit Out/ Local Hit Out Array 0. LHO[1] and LHO[0] are logically the same signal.
One of these signal is connected to one input on the LHI bus of the downstream devices
in a cascade.
When MultiSearch is performed, LHO[1:0] becomes LHO_0[1:0] (Local Hit output signals
for Array 0).
BHI[2:0]
I
Block Hit In. These signals are inputs from the last device in the upstream blocks in a
cascade that indicate whether there is a hit in the upstream/previous block(s).
BHO[2:0]
O
Block Hit Out. These signals are logically the same signal. One of these signals is
connected to one input on the BHI bus of the downstream devices in the downstream
blocks.
FULI[6:0]
LHI_1_L[6:0] (MSE=1)
I
Full In/Local Hit In Array 1. Each signal is driven by an upstream device’s FULO output
in a block to generate the FULL signal for that block. During a Search operation, these
signals indicate whether an upstream device had a free entry for a future Learn.
When MultiSearch is performed, FULI[6:0] becomes active Low LHI_1_L[6:0] (Local Hit
input signals for Array 1).
FULO[1:0]
LHO_1_L[1:0] (MSE=1)
O
Full Out/Local Hit Out Array 1. FULO[0] and FULO[1] are logically the same signal. One
of these signal is connected to one input on the FULO bus of the downstream devices in
a cascade.
When MultiSearch is performed, FULO[1:0] becomes active Low LHI_0_L[1:0] (Local Hit
output signals for Array 1).
Supplies
VDD
Core Supply: 1.2V.
VDD_PLL
PLL Block Supply: 1.2V.
VDDQ_ASIC
ASIC and Cascade Interface I/O Supply: 1.5V (HSTL) or 1.8V/2.5V (LVCMOS).
VDDQ_SRAM
SRAM Interfaced I/O Supply: 1.5V (HSTL) or 1.8V/2.5V (LVCMOS).
VDDQ_JTAG
JTAG Test Access Port I/O Supply: 2.5V (LVCMOS).
Test Access Port
TDI
I
Test access port test data in.
TCK
I
Test access port test clock.
TDO
T
Test access port test data out.
TMS
I
Test access port test mode select.
TRST_L
I
Test access port reset.
Notes:
2.
I = Input only, I/O = input or output, O = output only, T = three-state output.
3.
The rise time of PARERR_L will depend on the value of the pull-up resistance. Sufficient delay should be allotted for in the error routine after clearing the parity
error in the parity control register and before this pin is sampled as part of the next command. Recommended external pull-up resistance range: 4.7K
Ω to 47KΩ.
4.
Require an external pull-down resistor such as 47K
Ω or 100KΩ.
5.
These signals will output at the rising edge of CLK2X (both rising and falling edges of CLK1X) in a MultiSearch operation.
Table 4-1. Ayama™ 10000 Signal Description (continued)
Parameter
Type[2]
Description
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