CONFIDENTIAL
PRELIMINARY
CYNSE10512
CYNSE10256
CYNSE10128
Document #: 38-02069 Rev. *F
Page 15 of 153
4.0
Signals Description
Table 4-1 lists and describes all Ayama 10000 signals.
Table 4-1. Ayama™ 10000 Signal Description
Parameter
Type[2]
Description
Clocks and Reset
CLK_MODE
I
Clock Mode. Selects the clock source for the device. When set to Low, the device uses
both CLK2X and PHS_L for its clock sources. When pulled High (VDDQ_ASIC), the device
uses CLK1X for its clock source (PHS_L must be externally grounded).
CLK2X/CLK1X
I
Master Clock. CLK_MODE selects either the CLK2X or CLK1X as the clock input signal.
CLK1X
Input signals are sampled on both rising and falling edges.
Output signals can be driven on both falling and rising depending on the operation and
the device configuration.
CLK2X
Input signals are sampled on the rising edge.
Output signals are driven on the rising edge.
PHS_L
I
Phase. An input signal that must switch at half the frequency of CLK2X. This signal should
be pulled LOW when the device is in CLK1X mode. See Section 5.6, “Clocks,” on page 42.
RST_L
I
Reset. Driving RST_L LOW initializes the device to the default state. The device becomes
active stable 4 CLK1X (8 CLK2X) cycles after RST_L is driven High (90% threshold).
Configuration
CFG_L
I
Configuration. When CFG_L is set to Low, the device will tristate DQ[71:68].
ID[4:0]
I
Device Identification. The binary-encoded device identification for a depth-cascaded
system starts at “00000” and goes up to “11110”. “11111” is reserved as the broadcast
address which selects all NSEs in the cascade.
On a broadcast Read, only the device with the LDEV bit set to ‘1’ will respond.
Any ID bit that is to be set High must be connected to VDDQ_ASIC.
ASICSEL
I
ASIC IO Select. When this signal is pulled High (1.8V or 2.5V LVCMOS), the Command,
Data and Cascade buses will operate in LVCMOS mode. When tied to Low, the buses
will operate in HSTL mode.
Signals affected by ASICSEL selection:
Clocks: CLK2X/CLK1X, PHS_L, RST_L
Command and Data: CMD[10:0], CMDV, DQ[71:0], PAR[1:0], ACK, EOT, SSF, SSV,
MULTI_HIT
Cascade Interface: LHI[6:0], LHO[1:0], BHI[2:0], BHO[2:0], FULI[6:0], FULO[1:0], FULL
SRAMSEL
I
SRAM IO Select. When this signal is pulled High (1.8V or 2.5V LVCMOS), the SRAM
Interface will operate in LVCMOS mode. When tied to Low, the interface will operate in
HSTL mode.
Signals affected by SRAMSEL selection:
SADR[25:0], CE_L, WE_L, OE_L, ALE_L
HSVREF0
I
HSTL Reference Voltage. When ASICSEL is set to GND, this signal must be connected
to the HSTL reference voltage (VDDQ_ASIC/2). Otherwise, they should be left floating.
HSVREF1
I
HSTL Reference Voltage. Refer to HSVREF0 description.
PARERR_L[3]
O
Parity Error. This signal is updated when there is a Core parity error or DQ Bus parity
error. It is an Active-Low Open-Drain signal that requires an external pull-up resistor to
VDDQ_ASIC.
This signal is valid only after the device is fully initialized.
ASIC Interface / Command and Data Buses (LVCMOS or HSTL I/II)
CMD[10:0]
I
Command Bus. Bit[10:2] contains the command parameters and Bit[1:0] specifies the
command.
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