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CONFIDENTIAL
PRELIMINARY
CYNSE10512
CYNSE10256
CYNSE10128
Document #: 38-02069 Rev. *F
Page 97 of 153
cycle
CLK2X
CMDV
CMD[1:0]
CE_L
OE_L
CMD[10:2]
WE_L
1
cycle
2
cycle
3
cycle
4
cycle
5
cycle
6
cycle
7
cycle
8
cycle
9
cycle
10
PHS_L
SADR[M:0]
SSF
SSV
ALE_L
Search1Search2
10
10
Search1
Search3
A B A B A B A B
A B1B2 C1C2C3C4
DQ
D1
D3
Search2
10
D2
Hit
Miss
Search3
Miss
Figure 6-41. Timing Diagram for Mixed Search for Block 0 Winning Device
CMD[2]
the last A-cycle
CMPR[2] on B-cycles
Logic 0 for A-cycles
for x72 and x144
Logic 0 on
1st x288 A-cycle
Logic 1 on the
|(LHI[6:0])
0
0
LHO[1:0]
|(BHI[2:0])
0
0
BHO[2:0]
z
z
z
z
z
z
z
1
1
0
0
Addr
z
z
0
z
0
z
1
z
1
z
1
From the last
device in the
block
A
CFG = all zeroes for Non-Enhanced Mode
NES = 00 (binary) in all blocks for Enhanced Mode, x72 search
HLAT = 000 (binary), TLSZ = 10 (binary), LRAM = 0 (binary), LDEV = 0 (binary).
M = 25 for CYNSE10512, 24 for CYNSE10256, 23 for CYNSE10128
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