CONFIDENTIAL
PRELIMINARY
CYNSE10512
CYNSE10256
CYNSE10128
Document #: 38-02069 Rev. *F
Page 94 of 153
The following is the sequence of operation for a single 576-bit Search command (also refer to Subsection 6.2, “Command Bus
Parameters,” on page 50).
• Cycle A:
— Command Bus: The host ASIC drives CMDV HIGH and applies Search command CMD[1:0] = “10” (binary). CMD[2] must
be driven to logic 1 for the first three A-cycles and then driven to logic 0 for the final A-cycle for 576-bit search.
{CMD[10],CMD[5:3]} signals must be driven with the index to the GMR pair for use in this Search operation. Each of the
four A-cycles provide a GMR index to mask 144 bits of the data to be compared. CMD[7:6] signals must be driven with the
same bits that will be driven on SADR[24:23] for CYNSE10512, SADR[23:22] for CYNSE10256, SADR[22:21] for
CYNSE10128 by this device if it has a hit. CMD[8] must be driven HIGH for every A-cycle. CMD[9] is don’t care for this cycle.
— DQ Bus: At the same time in cycle A, DQ[71:0] must be driven with 72-bit data (which is part of the 576-bit data) to be
compared.
• Cycle B:
— Command Bus: The host ASIC continues to drive CMDV HIGH and to apply Search command CMD[1:0] = “10” (binary).
CMD[5:2] must now be driven by the index of the comparand register pair for storing the two 72-bit word presented on the
DQ bus during cycles A and B. Each of the four B-cycles provide an index for a pair of comparand register. CMD[8:6] signals
must be driven with the index of the SSR that will be used for storing the address of the matching entry and hit flag (see
page 27 for a description of SSR[0:7]). CMD[10:9] are don’t cares for this cycle.
— DQ Bus: The DQ[71:0] continues to carry the 72-bit data (which is part of the 576-bit data) to be compared.
Note. For 576-bit searches, the host ASIC must supply individual 72-bit data on DQ[71:0] during cycles A and B. Also, four
individual pairs of GMR and CMPR registers may be involved in the comparison.
The logical 576-bit Search operation is shown in Figure 6-38. The upper half of the device consisting of 576-bit entries is compared
to a 576-bit search key, K that is presented on the DQ bus in eight CLK2x cycles using the GMR and local mask bits. The same
also happens in the lower half of the device. The GMR is the 576-bit word specified by four pairs of GMRs selected by GMR
indices in each of the eight devices. The 576-bit word K (presented on the DQ bus in all eight cycles of the command) is also
stored in both even and odd comparand register pairs (selected by the comparand register index in command cycle B) in each
of the eight devices. The word K is compared with each entry in the table in both arrays. The winning addresses from both arrays
will be determined based on the Soft Priority and Mini-Key scheme, and the result of the two searches from the two halves are
driven as part of the SRAM address on the SADR[N:0] lines (N = 25 for CYNSE10512, 24 for CYNSE10256, 23 for CYNSE10128)
with two SRAM cycles as shown in the timing diagram (see Section 6.7, “SRAM PIO Access,” on page 121). On a global miss
cycle, the device with LRAM = 1 (binary) (default driving device for the SRAM bus) and LDEV = 1 (binary) (default driving device
for SSF and SSV signals) will be the default driver for such missed cycles.
The Search command is a pipelined operation and executes a Search at one-eighth the rate of the frequency of CLK2X for 576-bit
searches in ×576-configured tables. The latency of the Search from command to SRAM access cycle is 5 for up to eight devices
in the table (TLSZ = 01 (binary)). SSV and SSF also shift further to the right for different values of HLAT, as specified in Table 6-5.
576
0
Location
0
1
2
3
N/2 - 1
(576-bit configuration)
address
K
GMR
576
0
(First matching
La
Figure 6-38. ×576 Table with Eight Devices
entry in the upper
576
0
Location
N/2
N/2 + 1
N/2 + 2
N/2 + 3
N - 1
address
K
GMR
576
0
(First matching
Lb
entry in the lowe
half)
half)
Upper Half (array 0)
Lower Half (array 1)
N = 262144 for CYNSE10512
131072 for CYNSE10256
65536 for CYNSE10128
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