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CONFIDENTIAL
PRELIMINARY
CYNSE10512
CYNSE10256
CYNSE10128
Document #: 38-02069 Rev. *F
Page 91 of 153
B
Multi Search2
10
10
10
A B A B A
A B
cycle
CLK2X
CMDV
CMD[1:0]
DQ
CE_L
OE_L
CMD[10:3]
WE_L
1
cycle
2
cycle
3
cycle
4
cycle
5
cycle
6
cycle
7
cycle
8
cycle
9
cycle
10
HLAT = 000 (binary), TLSZ = 01 (binary), LRAM = 0 (binary), LDEV = 0 (binary).
Note: |(LHI_0[6:0]) and &(LHI_1_L[6:0]) stands for the boolean ‘OR’ and ‘AND’ of the entire LHI bus.
Note: Each bit in LHO_0[1:0] and LHO_1_L[1:0] is the same logical signal.
PHS_L
SADR[M:0]
SSF
SSV
ALE_L
Multi Search1
Multi Search3
z
z
z
z
z
z
z
0
0
0
1
1
1
(LHI_0[6:0])
0
LHO_0[1:0]
cycle
11
cycle
12
cycle
13
cycle
14
cycle
15
cycle
16
A B A B A B A B A B A B A B A B
A6
A1 A2 A3A4 A5
A7A8B1 B2 B3B4 B5 B6B7B8C1C2C3C4 C5C6C7C8
0
z
z
z
z
z
z
1
CMD[2]
the 4th A-cycle
CMPR[2] on B-cycles
Logic 1
for 3 A-cycles
Logic 0 on
Multi-Search1
Multi-Search2 (Miss
on this device)
Multi-Search3 (Miss
on this device)
&(LHI_1_L[6:0]) 1
LHO_1_L[1:0]
1
0
1
(Hit in both arrays)
Figure 6-35. Timing Diagram for 576-bit MultiSearch Device Number 0
Addr
A
Addr
A
M = 25 for CYNSE10512, 24 for CYNSE10256, 23 for CYNSE10128
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