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CONFIDENTIAL
PRELIMINARY
CYNSE10512
CYNSE10256
CYNSE10128
Document #: 38-02069 Rev. *F
Page 87 of 153
B
Search2
10
10
10
A B A B A
A B
cycle
CLK2X
CMDV
CMD[1:0]
DQ
CE_L
OE_L
(Miss on
CMD[10:3]
WE_L
1
cycle
2
cycle
3
cycle
4
cycle
5
cycle
6
cycle
7
cycle
8
cycle
9
cycle
10
HLAT = 000 (binary), TLSZ = 01 (binary), LRAM = 0 (binary), LDEV = 0 (binary).
Note: |(LHI[6:0]) stands for the boolean ‘OR’ of the entire bus LHI[6:0].
Note: Each bit in LHO[1:0] is the same logical signal.
PHS_L
SADR[M:0]
SSF
SSV
ALE_L
Search1
Search3
Search1
Search3
Addr
z
z
z
z
z
z
z
0
0
0
1
1
1
this device)
|(LHI[6:0])
is the global
(Miss on
this device)
LHO[1:0]
Search2
(This device
Figure 6-32. Timing Diagram for 576-bit Single Search Device Number 1
cycle
11
cycle
12
cycle
13
cycle
14
cycle
15
cycle
16
A B A B A B A B A B A B A B A B
A6
A1 A2 A3A4 A5
A7A8B1 B2 B3B4 B5 B6B7B8C1C2C3C4 C5C6C7C8
0
z
z
z
z
z
z
0
0
winner)
1
1
CMD[2]
the 4th A-cycle
CMPR[2] on B-cycles
Logic 1
for 3 A-cycles
Logic 0 on
B
M = 25 for CYNSE10512, 24 for CYNSE10256, 23 for CYNSE10128
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