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CONFIDENTIAL
PRELIMINARY
CYNSE10512
CYNSE10256
CYNSE10128
Document #: 38-02069 Rev. *F
Page 80 of 153
cycle
CLK2X
CMDV
CMD[1:0]
CE_L
OE_L
CMD[10:2]
Search2
Search4
WE_L
1
cycle
2
cycle
3
cycle
4
cycle
5
cycle
6
cycle
7
cycle
8
cycle
9
cycle
10
HLAT = 001 (binary), TLSZ = 10 (binary),
LRAM = 0 (binary), LDEV = 0 (binary).
Note: |(BHI[2:0]) stands for the boolean ‘OR’ of the entire bus BHI[2:0].
Note: |(LHI[6:0]) stands for the boolean ‘OR’ for the entire bus LHI[6:0].
Note: Each bit in BHO[2:0] is the same logical signal.
Note: Each bit in LHO[1:0] is the same logical signal.
PHS_L
SADR[M:0]
SSF
SSV
ALE_L
Search1
Search2
Search4
10
10
10
10
Search1
Search3
A B A B A B A B
z
z
z
z
z
z
LHO[1:0]
0
I(BHI[2:0])
0
Search3
|(LHI[6:0])
0
BHO[2:0]
0
z
W1W2X1X2 Y1 Y2Z1 Z2
DQ
D1
D2
D3
D4
(Miss on
this device)
(Miss on
this device)
(Miss on
this device)
(Miss on
this device)
Figure 6-26. 144-bit Search Timing Diagram for Devices Above Block #3 Winning Device
M = 25 for CYNSE10512, 24 for CYNSE10256, 23 for CYNSE10128
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